JPS5854725A - Delay circuit - Google Patents

Abstract

PURPOSE:To obtain a delay circuit which can set delay time speedily by connecting a resistive element to an input terminal and connecting a transmission line with opened receiving end having an impedance equal to the resistance value to the element. CONSTITUTION:When an input signal is given, an inversion signal of the input signal appears with a delay of a dfG1 to an output of a gate G1. An output of a resistive element 2 does not reach a voltage level of the inversion signal immediately, but remains at a signal level of a half the amplitude of the inversion signal by a time of d2l where the length of a transmission line 3 provides for the propagation of signal. When the signal level drops to V1, a Schmitt circuit G2 is driven and a high level is outputted with a delay of drG2. Further, the output signal disappears after a delay of time Df0 in delay time 4 from the start of drop of the input signal. Thus the Df0 and Dr0 can be changed by changing the length l of the transmission line 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay circuit using a transmission line with an open receiving end.

Conventionally, when determining the timing of a computer's logic circuit or clock system, the delay time from the transmitting gate to the receiving gate is determined by gradually changing the length of the line connecting the gates included in them through trial and error. A circuit is used that is formed by adjusting the value to an appropriate value.

The formation of this circuit is primitive, unaffected by power fluctuations,
Although it is highly reliable, the counter-questions and the formation process are troublesome, and the formation is time-consuming and not speedy as it depends on human hands.

The present invention was devised in view of the drawbacks of the conventional circuits described above, and its purpose is to quickly set the delay time.
The purpose of this invention is to provide a delay circuit that can be used.

Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.

Figure 1 shows the configuration of the circuit of the present invention. (1) is a terminal, a gate (G1) is connected to this, and a resistive element such as a resistor (2) is connected to the output (input of the circuit of the present invention). Connected. A transmission line (3) with an open receiving end and a Schmitt circuit (G2) are connected to the output of this resistive element (2) to constitute a delay circuit (4) of the present invention. This delay 1
The impedance of the transmission line (3) of the circuit (4) is made equal to the resistance 111 of the resistive element.

The operation of the delay circuit (4) having the above configuration will be explained.

When a human input signal as shown in (2-1) in FIG. 2 is input to the terminal (+1), an inverted signal of the input signal appears at the output of the gate (G1) with a delay of the fall delay time (dfGl). The inverted signal is propagated to the output of the resistive element (2). Since the transmission line (3) having the same impedance is connected, the output of the resistive element (2) does not immediately reach the voltage level of the inverted signal, and the length of the transmission line (3) The signal level remains at half the amplitude of the inverted signal for the delay time d2t given to the propagation, and after the delay time has passed, the signal level drops to the amplitude of the inverted signal (see Figure 2). (See (2-2)). During the drop, the threshold voltage (1) of the Schmitt circuit (G) is passed, so the Schmitt circuit (G2) is driven at that time. Schmitt circuit (G2) rise time (drG
After a delay of 2), the signal that had been at a low level at its output becomes a high level signal (see (2-3) in FIG. 2). Therefore, the delay time (DrO) at output signal generation 1 of this delay circuit (4) is (■)ro += dfGl +t12L +tirG2
・It becomes -(+).

Then, the delay between 1 and i (D
fO) occurs, and after a delay of this time, the signal disappears from the output of the enhancement circuit (4). voltage). 'N sail time I), 7'Oba]) f
o=drGI-1-d21.
+ dj'G2 = 12) and Namu (-
1 In equation (2), drGl is the vertical position of the gate (G,).
1 - delay time, d f c 2 ), -i falling delay time of Schmitt circuit (G2), formula +11.
(As can be seen from 21, by changing the length l of the transmission line (3), (Dro), (1)fo) can be changed. Changing the length t can be carried out very easily in the delay time measurement state. For example, you can cut the transmission line to an appropriate length from its open end.1. Therefore, the delay time of the delay circuit can be set quickly1. Figure 3 shows a chopper circuit (
5) is shown. In this circuit, (G3) is a NAND circuit, and other constituent elements are the same as those in the circuit shown in Figure 1, so the same reference numbers are given to the same constituent elements.
Therefore, the explanation will be omitted.

The operation of the delay circuit (4) in this chopper circuit is as follows.
The signal waveform diagram is the same as that explained for path 01, and the signal waveform diagram is (4-1,), (4-2), (4-3) in Figure 4.
It is shown in These figures correspond to (2) in Figure 2, respectively.
-1), (2-2), and (2-3).

Then, by supplying the output signal of the delay circuit (4) and the human input signal to the terminal (1) to the NAND circuit (G3), a chopper output signal as shown in (4-4) in Fig. 4 is obtained. do.

The pulse width WO of this output signal is Wo=-dj'as+d
fGl+d2t+dfa20drG3・・・・・・・・・
・(3) becomes. However, dfG3 is the falling delay time of the NAND circuit (G3), dfGl is the falling delay time of the gate (G1), and dras is the rising delay time of the NAND circuit (G3), and the others are the same as described above.

As can be seen from equation (3), the length of the transmission line (3) is t
) of the chopper circuit (5) by changing the pulse width (WO
) can be changed. Changing the length 1) can be achieved very easily in the pulse width measurement state. For example, the transmission line (3) may be cut to an appropriate length from its open end. Therefore, the pulse width of the chopper circuit (5) can be set quickly.

FIG. 5 shows an expander (6) constructed using the delay circuit (4) of FIG. In Figure 5, (G4)
is an OR circuit, and the other components are the same as those in FIG. 1, so the same reference numerals are given to the same components and the explanation thereof will be omitted.

The operation of the delay circuit (4) used in this expander is similar to the circuit shown in Figure 1, and its signal waveform diagrams are shown in (6-1), (6-2), and (6-3) in Figure 6. These figures are shown in (2-1) of Figure 2, respectively.
, (2-2) and (2-3).

Then, the output signal of the delay circuit (4) and the input signal to the terminal (1) are supplied to the OR circuit (G4) as shown in FIG.
An expander output signal as shown in 6-4) is obtained.

Pulse I1m (Wl) of this expander output signal W1==drc4-1-drc1+d2L+dfG2+
dfG4・・・・・・(4) Totoru. However, in equation (4), drG4 is the rise delay time of the OR circuit (G4), and dfG4 is the OR circuit (G4).
), and the rest is the same as that described for the circuit of FIG.

As can be seen from equation (4), the length of the transmission line (3) is t
) can change the pulse width of the expander (6). Further, the length t) can be changed very easily in the pulse width measurement state. For example, the transmission line (3) may be cut to an appropriate length from its open end. Therefore, the pulse width of the expander (6) can be set quickly.

In short, according to the present invention, the circuit can be
Measurements are made in the state of

[Brief explanation of the drawing]

FIG. 1 is a delay circuit diagram of the present invention, and FIG. 2 is a delay circuit diagram of the present invention.
1. To explain the operation of the circuit, 11 is a waveform diagram, 3rd diagram is a Chompa circuit diagram, 4th diagram is a signal waveform diagram to explain the operation of the circuit, and 5th diagram is a diagram showing an expander. FIG. 6V is a signal waveform diagram for explaining the operation of the expander of FIG. 5. In the figure, (2) is a resistive element, (3) is a transmission line, and (G
2) 1. Schmitt circuit reduces). Patent applicant: Fujitsu Limited Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] A resistive element is connected to the input, the output terminal has an impedance equal to the resistance value of the resistive element, and a Schmitt circuit is connected to a transmission line with an open receiving end. delay circuit.