JPS6411434A - Data transmission equipment - Google Patents

Data transmission equipment

Info

Publication number
JPS6411434A
JPS6411434A JP62165260A JP16526087A JPS6411434A JP S6411434 A JPS6411434 A JP S6411434A JP 62165260 A JP62165260 A JP 62165260A JP 16526087 A JP16526087 A JP 16526087A JP S6411434 A JPS6411434 A JP S6411434A
Authority
JP
Japan
Prior art keywords
clock
circuit
sent
abnormality information
master station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62165260A
Other languages
Japanese (ja)
Inventor
Atsushi Morioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62165260A priority Critical patent/JPS6411434A/en
Publication of JPS6411434A publication Critical patent/JPS6411434A/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To instantaneously judge trouble occurrence on a master station side and to prevent ineffective data transmission from being performed by providing a sent clock generating circuit on a slave station side and sending and abnormality information frame to a master station in synchronizingly with a clock generated by said circuit. CONSTITUTION:When a slave station receives no clock owing to trouble occurrence, a received clock break detecting circuit 12 detects a clock break and supplies detection signals 26 and 27 to a sent clock switching circuit 14 and a sent data switching circuit 15. The circuit 14 switches the selection of a sent clock from a sent-back clock circuit 17 to the sent clock generating circuit 16. At this time, the circuit 16 generates the sent clock 28 of the same frequency with a clock received in a normal state. Further, the circuit 15 switches the selection of sent data from a transmission circuit 18 to an abnormality information frame generating circuit 19. At this time, the circuit 19 generates the abnormality information clock 29. This frame 29 is sent to the master station through a transmission line 11 by using the clock 28.
JP62165260A 1987-07-03 1987-07-03 Data transmission equipment Pending JPS6411434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165260A JPS6411434A (en) 1987-07-03 1987-07-03 Data transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62165260A JPS6411434A (en) 1987-07-03 1987-07-03 Data transmission equipment

Publications (1)

Publication Number Publication Date
JPS6411434A true JPS6411434A (en) 1989-01-17

Family

ID=15808945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165260A Pending JPS6411434A (en) 1987-07-03 1987-07-03 Data transmission equipment

Country Status (1)

Country Link
JP (1) JPS6411434A (en)

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