JPS647737A - Loop back test system for signal converting interface - Google Patents

Loop back test system for signal converting interface

Info

Publication number
JPS647737A
JPS647737A JP62160869A JP16086987A JPS647737A JP S647737 A JPS647737 A JP S647737A JP 62160869 A JP62160869 A JP 62160869A JP 16086987 A JP16086987 A JP 16086987A JP S647737 A JPS647737 A JP S647737A
Authority
JP
Japan
Prior art keywords
circuit
test
signal
test signal
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62160869A
Other languages
Japanese (ja)
Inventor
Nagayasu Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62160869A priority Critical patent/JPS647737A/en
Publication of JPS647737A publication Critical patent/JPS647737A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To eliminate the institution of a test signal receiving and transmitting circuits on all signal converting interface parts by providing a common test signal outgoing circuit and a common test receiving circuit at a loop back test circuit. CONSTITUTION:When a signal converting circuit 12 of a signal converting interface part 2 for the external signal of an attribute A is tested, a common test signal outgoing circuit 14 of the loop back test circuit 1 is excited, a common test signal is generated, and the test signal of the attribute A is generated at a test signal outgoing circuit 6 of the interface part 2. The test signal of the attribute A is communicated to the circuit 12, converted, inverted, folded, and a test result is decided at a test receiving circuit 9, and when the result is normal, a gate circuit 16 is opened. The common test signal sent to a multiple bus 4 is loop-backed at a circuit 16 and returned to a multiple bus 5, only when the test result is normal. The signal is received at a common test receiving circuit 15, and the normally of the circuit 12 is detected.
JP62160869A 1987-06-30 1987-06-30 Loop back test system for signal converting interface Pending JPS647737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62160869A JPS647737A (en) 1987-06-30 1987-06-30 Loop back test system for signal converting interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62160869A JPS647737A (en) 1987-06-30 1987-06-30 Loop back test system for signal converting interface

Publications (1)

Publication Number Publication Date
JPS647737A true JPS647737A (en) 1989-01-11

Family

ID=15724128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62160869A Pending JPS647737A (en) 1987-06-30 1987-06-30 Loop back test system for signal converting interface

Country Status (1)

Country Link
JP (1) JPS647737A (en)

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