JPS6410926B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer printed capacitor, and its purpose is to simultaneously print a large number of electrodes and then cut them into a large number of chip capacitors or composite capacitors. The object of the present invention is to provide a manufacturing method that requires less waste.

1 to 3 show a conventional manufacturing method. This conventional example shows a four-sided case, in which counter electrodes _{1, 2, and 3, which are necessary to form two capacitors C 1} and C ₂ after completion, are printed on each of four sides within the same substrate 4, and the first In the figure, the counter electrode 3 indicated by diagonal lines and the counter electrodes 1 and 2 indicated without diagonal lines are the second
As shown in the figure, the printing layers are different and are not printed at the same time. The printing process for the counter electrodes 1, 2, and 3 is as follows:
First, as shown in FIG. 3a, electrodes 1a, 1b, 1c, and 1d as the counter electrode 1 are arranged symmetrically on the dielectric substrate 5 with the pattern matching the electrodes 2a, 2b, 2c, and 2d as the counter electrode 2. After that, a dielectric layer 6 is formed on the electrodes 1a, 1b, 1c, and 1d, and the lower electrodes 1a to 1d and 2a to 2d are printed on this dielectric layer 6 as shown in FIG. 3b. Correspondingly, electrodes 3a, 3b, 3c, and 3d as the counter electrodes 3 are printed, and a dielectric layer is further formed on the electrodes 3a to 3d in FIG. 3b to form the lower electrodes as in FIG. 3a. 1a
Counter electrodes 1 and 2 are printed corresponding to 1d and 2a to 2d. Next, the material shown in FIG. 1 obtained by repeating steps a and b in FIG. 3 is dried and then cut along the broken line AB in FIG.
1b, 1c and 1d, and a broken line CD, so that the end face of each lead-out part 7 of the electrodes 2a to 2d, 3a to 3d is surely exposed to the cut end face.
Further cuts are made at C'-D', E-F, and G-H. Each of the capacitor chips thus divided into four parts is coated with conductive paste on the end faces of the lead-out portions 7 of the electrodes 1a to 1d, 2a to 2d, and 3a to 3d of each layer exposed on the end faces of the chip, as shown in Fig. 2. 8 and terminals 9a and 9 in the equivalent circuit of FIG. 1b.
b, 9c are formed. Furthermore, a conductive paste 8 is applied to the chip end face 10 where none of the lead-out portions 7 are exposed in order to be used as a relay terminal for connection between other components. Note that a point 11 in FIG. 2 indicates a connection point between the conductive paste 8 and the opposing electrodes 1 and 3 of each layer.

Note that there are four capacitor chip areas a, b, c,
If the designs of the opposing electrodes 1 to 3 in D are swapped in the capacitor chip areas A, B, C, and D, there will be some printing pressure between each block because each block will not have the same shape. , which tends to cause variations in capacity. When the patterns are matched as shown in FIG. 1, each piece undergoes the same process, so variations in capacitance are minimal. However, a large amount of waste C-D-D'-C' is generated, resulting in a loss. Here, we are explaining the case of four-sided cutting, but if this becomes a multi-piece cutting or the pattern becomes complicated, this problem becomes difficult to solve, and in the end, a lot of waste is created. becomes.

Therefore, the present invention prints the electrodes of each capacitor in each capacitor chip area on the same substrate, with a part of this electrode penetrating into the adjacent capacitor chip area, and this part leaving the intruded part in the adjacent capacitor chip area. By cutting, the amount of waste for cutting the substrate can be reduced, and the manufacturing method of the present invention will be explained below based on a specific embodiment shown in FIGS. 4 to 8. Components having the same functions as those in FIGS. 1 to 3 are designated by the same reference numerals, and their explanations will be omitted.

In Figure 4, broken lines A-B, C-D, E-F,
Counter electrodes 1, 2, and 3 are located in the four capacitor chip areas A, B, C, and D surrounded by the cutting line G-H.
is printed with the drawer 7 inserted into the adjacent capacitor chip area. That is, looking at the capacitor chip areas A and C, the lead-out portions 7 of the electrodes 1a and 1c are located in the capacitor chip areas A and C, respectively.
As can be seen from FIG. 8, which will be described later, the electrodes 2a and 3c are printed with the tips of the lead-out portions 7 entering the capacitor chip areas H and B, respectively. Also, regarding the capacitor chip areas b and d, the tips of the lead-out portions 7 of the electrodes 2b and 3d are located in the capacitor chip area similarly to the electrodes 2a and 3c.
It is printed by entering the country.

The substrate 4 printed in this way and laminated as shown in FIG.
The tips of the capacitor chips are left in the capacitor chip areas B and D. The substrate 4 is also cut at the cut plane IJ along the broken line IJ, so that the lead-out portions 7 of the electrodes 1b and 1d are exposed at the end surface. Furthermore, the substrate 4 is also cut along the broken line CD, and as shown in FIG. In the chip area A, the electrode 2a
The tip of the lead-out part 7 of the electrode 3c remains between the lead-out parts 7 of the electrode 3c. This also applies to capacitor chip areas B and D.

Each capacitor chip is divided into capacitor chips in this way, and conductive paste is pasted on each end face as before.
AgPd (silver palladium paste) is applied, but in the present invention, the tips of the remaining electrodes 1a or 1c are exposed on the chip end face 10 in FIG. 2 as shown in FIG. 6b. Drawer part 7
The tip of the chip is terminated by the applied conductive paste 8 as shown in FIG. 7, and the adhesive strength of the conductive paste 8 on the chip end face 10 is increased. Further, the tip of the remaining drawn-out portion 7 exposed at the cut surface 12 along the broken line CD is the electrode 2a or 3c, 2
Since it is terminated with the conductive paste 8 together with the lead-out portion 7 of the chip end face 12 as shown in FIG. 8, the adhesive strength of the conductive paste 8 on the chip end face 12 is also increased.

Furthermore, in the capacitor chips in capacitor chip areas B and D, an appropriate small capacitance C ₀ is formed between the remaining lead-out portion 7 and the electrode 1b or 1d, as shown in FIG. A new capacitor is obtained.

In addition, although the case of four chamfering was mentioned as an example and demonstrated in the said Example, this is not limited to four chamfering. Further, in the above embodiment, the termination was performed using a conductive paste, but the connection may also be performed by vapor deposition or the like.

As explained above, according to the manufacturing method of the present invention,
In order to print a part of the electrode into the adjacent capacitor chip area, the dashed line C-
Instead of cutting along the two cutting lines D and C'-D', each electrode can be exposed on the end faces of both capacitor chips by simply cutting along one cutting line, the broken line CD. This can be eliminated and a new capacitor of small capacity can be obtained.

[Brief explanation of the drawing]

Figures 1a and b are a plan view of the board and the equivalent circuit of each capacitor chip, Figure 2 is a side view of each capacitor chip, Figures 3a and b are explanatory diagrams of Figure 1a, and Figure 4 is an explanatory diagram of Figure 1a.
8 shows an embodiment of the present invention, FIG. 4 is a plan view of a substrate in the manufacturing method of the present invention, FIG. 5 is a sectional view taken along line XX in FIG. 4, and FIGS. The figure is a manufacturing process explanatory diagram, and FIG. 9 shows an equivalent circuit. DESCRIPTION OF SYMBOLS 1, 2, 3... Counter electrode, 4... Substrate, 7... Lead-out part, 8... Conductive paste, 9a-9c... Capacitor terminal, I--2... Capacitor chip area.

Claims (1)

[Scope of Claims] 1. When a part of a capacitor electrode, which is created by forming and laminating a plurality of capacitor electrodes on a dielectric material on the same substrate, is cut into a chip shape, adjacent A method for manufacturing a multilayer printed capacitor in which a part of the electrode is formed on a chip. 2. A method for manufacturing a multilayer printed capacitor according to claim 1, wherein a plurality of electrodes forming a capacitor are printed within a chip-shaped substrate.