JPS6410367A - Input and output control device - Google Patents
Input and output control deviceInfo
- Publication number
- JPS6410367A JPS6410367A JP62165537A JP16553787A JPS6410367A JP S6410367 A JPS6410367 A JP S6410367A JP 62165537 A JP62165537 A JP 62165537A JP 16553787 A JP16553787 A JP 16553787A JP S6410367 A JPS6410367 A JP S6410367A
- Authority
- JP
- Japan
- Prior art keywords
- output
- input
- control information
- memory
- controllers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE:To prevent missing of common use control information at interruption of power supply by writing common control information into plural memories provided onto plural memories provided on the input/output controller applying common use control so as to multiplex the common use control information in writing the common use control information into the memories. CONSTITUTION:With a power supply for the 1st and 2nd input/output controllers turned on, an output signal 117 of a state setting circuit 63 set to output '1' from the 1st input/output controller and to output '0' from the input/output controllers, an output of a first-come discrimination circuit 11 having an output signal 117 of the state setting circuit 63 whose level is logical 1 is used for the both. In setting '1' to a first-come discrimination request register 60, an output 114 of a switching circuit 61 of the input/output controller receiving the signal earlier goes to '1', a value of a register 62 is outputted to an external connection bus 106 and the memory of the 1st and 2nd input/output controllers is accessed. That is, an address, a data and a control signal are transmitted/received to/from an external connection bus 106, and the data is read from the memory in the input/output controllers applying write/readout of the data to/from the memory 12 of 1st and 2nd input/output controllers to apply duplication of the common share memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62165537A JPS6410367A (en) | 1987-07-03 | 1987-07-03 | Input and output control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62165537A JPS6410367A (en) | 1987-07-03 | 1987-07-03 | Input and output control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6410367A true JPS6410367A (en) | 1989-01-13 |
Family
ID=15814270
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62165537A Pending JPS6410367A (en) | 1987-07-03 | 1987-07-03 | Input and output control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6410367A (en) |
-
1987
- 1987-07-03 JP JP62165537A patent/JPS6410367A/en active Pending
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