JPS6410332A - Pipeline control system - Google Patents

Pipeline control system

Info

Publication number
JPS6410332A
JPS6410332A JP16533487A JP16533487A JPS6410332A JP S6410332 A JPS6410332 A JP S6410332A JP 16533487 A JP16533487 A JP 16533487A JP 16533487 A JP16533487 A JP 16533487A JP S6410332 A JPS6410332 A JP S6410332A
Authority
JP
Japan
Prior art keywords
stage
signal
stack
processing unit
full
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16533487A
Other languages
Japanese (ja)
Inventor
Shigeko Yazawa
Yuji Aoki
Akihiro Tamano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16533487A priority Critical patent/JPS6410332A/en
Publication of JPS6410332A publication Critical patent/JPS6410332A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To realize the continuous transmission of request signals from an instruction control unit by making each stage in a pipeline processing unit function as a stack. CONSTITUTION:A signal REQA is sent to the next processing unit only when an AND circuit 15 detects that a valid bit 24 of the final stage 14 of a pipeline is set at 1 and no signal FULL is transmitted from a request A counter 19. The stage 14 is set after detecting that a stack 6 of a following stack processing unit 3 has an idle area owing to no transmission of the signal FULL. Thus the stage 14 is set under the condition that no FULL signal is transmitted from the counter 19 ad at the same time the bit 24 is equal to 1. While a stage 13 sends the processing element held by the stage 14 as soon as a new processing element is set.
JP16533487A 1987-07-03 1987-07-03 Pipeline control system Pending JPS6410332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16533487A JPS6410332A (en) 1987-07-03 1987-07-03 Pipeline control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16533487A JPS6410332A (en) 1987-07-03 1987-07-03 Pipeline control system

Publications (1)

Publication Number Publication Date
JPS6410332A true JPS6410332A (en) 1989-01-13

Family

ID=15810358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16533487A Pending JPS6410332A (en) 1987-07-03 1987-07-03 Pipeline control system

Country Status (1)

Country Link
JP (1) JPS6410332A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5069953A (en) * 1990-05-17 1991-12-03 Gunze Limited Heat-shrinkable foamed composite film and process for preparation of same
EP1703376A2 (en) 2005-03-16 2006-09-20 Fujitsu Limited Pipeline processor with queue busy judgement; program and recording medium for the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5069953A (en) * 1990-05-17 1991-12-03 Gunze Limited Heat-shrinkable foamed composite film and process for preparation of same
EP1703376A2 (en) 2005-03-16 2006-09-20 Fujitsu Limited Pipeline processor with queue busy judgement; program and recording medium for the same
CN100414495C (en) * 2005-03-16 2008-08-27 富士通株式会社 Information processing system,pipeline processor and computer readable recording medium

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