JPS639657B2 - - Google Patents
Info
- Publication number
- JPS639657B2 JPS639657B2 JP54142491A JP14249179A JPS639657B2 JP S639657 B2 JPS639657 B2 JP S639657B2 JP 54142491 A JP54142491 A JP 54142491A JP 14249179 A JP14249179 A JP 14249179A JP S639657 B2 JPS639657 B2 JP S639657B2
- Authority
- JP
- Japan
- Prior art keywords
- spacer
- film
- reel
- semiconductor chip
- film carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 125000006850 spacer group Chemical group 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 19
- 239000000969 carrier Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Packages (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特に半
導体チツプを搭載したフイルムキヤリアをリール
に巻いたり、フイルムキヤリアを重ねる場合フイ
ルムキヤリアどうしが接触しないように用いるフ
イルムキヤリアのスペーシング方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and particularly for winding a film carrier carrying a semiconductor chip onto a reel, or when stacking film carriers, the present invention relates to a method for manufacturing a semiconductor device. Concerning pacing methods.
半導体チツプの自動ボンデイング化、装置実装
の高密度化の促進の一つとして、フイルムキヤリ
ア方式が採用されるようになつてきた。このよう
なフイルムキヤリア方式は従来のワイヤを使用し
て半導体チツプと外部を接続するのではなく、フ
イルム上へリードを設けリードと半導体チツプの
接続部（バンプ）をチツプ単位に一括してボンデ
イングする方式である（以下フイルムキヤリア方
式）。このフイルムキヤリア方式は種々の製造工
程、運搬手段、出荷方法でリールに巻いて行なう
ことが出来る特徴を持つている。その場合、フイ
ルムキヤリアとフイルムキヤリアが接触してチツ
プにキズが生じたり、チツプをボンデイングして
あるリードが変形してオープンまたは他のリード
とシヨートしないようにスペーサを入れて間隔を
保つ方法が取られている。 Film carrier methods have come into use as a way to promote automatic bonding of semiconductor chips and higher density device packaging. This type of film carrier method does not use conventional wires to connect the semiconductor chip to the outside, but instead creates leads on the film and bonds the connections (bumps) between the leads and the semiconductor chip all at once on a chip-by-chip basis. (hereinafter referred to as film carrier method). This film carrier method has the feature that it can be wound onto a reel in various manufacturing processes, transportation means, and shipping methods. In this case, it is recommended to insert a spacer to maintain the distance between the film carriers to prevent them from coming into contact and damaging the chip, or from deforming the leads bonded to the chip and causing them to open or shoot with other leads. It is being
このスペーサとして従来はポリエステルの絶縁
性スペーサであつた。この絶縁性スペーサを使用
した場合、リールからリールへ巻きかえたり運搬
による振動の摩擦のため静電気がスペーサに発生
し、その高電圧によりキヤリアフイルム上にボン
デイングされた半導体チツプを電気的不良にする
欠隔があつた。又、スペーサから直接圧力が半導
体チツプに加わると半導体チツプやそれにつらな
るリードを破損する恐れもある。 Conventionally, this spacer has been an insulating spacer made of polyester. When this insulating spacer is used, static electricity is generated in the spacer due to vibration friction caused by rewinding from reel to reel and transportation, and this high voltage can cause electrical failure of the semiconductor chips bonded on the carrier film. There was a gap. Furthermore, if pressure is applied directly to the semiconductor chip from the spacer, there is a risk of damaging the semiconductor chip and the leads connected to it.
本発明の目的は前記破壊の欠陥を排除したフイ
ルムキヤリアのスペーシング方法を提供すること
にある。 SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for spacing film carriers that eliminates the above-mentioned destructive defects.
本発明は、重なり合うフイルム間に両側に凹凸
加工部のある導電性を有するスペーサを用いる点
にある。 The present invention is characterized in that a conductive spacer having concave and convex portions on both sides is used between overlapping films.
次に図面により本発明を説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の実施例を示す図である。リー
ル１に巻いたフイルムキヤリア２とフイルムキヤ
リア２どうしが接触しないようにそれらの間へ導
電性スペーサ３を使用した一実施例である。前記
スペーサ３の両側にはフイルムキヤリア上の中心
部にあるチツプ５、リード６に対してスペーサか
らの圧力が直接加わらないように空隙を持たせる
ため凹凸に加工した凹凸が加工部４を形成してあ
る。すなわち第２図にスペーサ３を介して上下に
フイルムキヤリア２が重なつた状態を示してい
る。ここでは直線状に示しているが第１図のよう
にリールにまかれているときは全体が円弧状にな
る。ここで第２図Ａは側面図、第２図Ｂは上面図
である。スペーサ３は両側の凹凸加工部４と中央
の平担部３′からなつている。２枚のフイルムキ
ヤリア２，２およびこれらフイリムキヤリアとス
ペーサとはスペーサ３の両側の凹凸加工部４が密
着することによつて、空間を保つており、スペー
サ３の平担の中央部３′はフイルムキヤリア２、
半導体チツプ５とは接していないから、半導体チ
ツプにスペーサから直接圧力が加わることはな
い。 FIG. 1 is a diagram showing an embodiment of the present invention. This is an embodiment in which a conductive spacer 3 is used between the film carrier 2 wound on the reel 1 and the film carrier 2 so that they do not come into contact with each other. On both sides of the spacer 3, a processed portion 4 is formed by processing irregularities to provide a gap so that pressure from the spacer is not directly applied to the chip 5 and lead 6 located at the center of the film carrier. There is. That is, FIG. 2 shows a state in which film carriers 2 are stacked one above the other with spacers 3 in between. Although it is shown in a straight line here, when it is wound on a reel as shown in Fig. 1, it becomes an arc shape as a whole. Here, FIG. 2A is a side view, and FIG. 2B is a top view. The spacer 3 consists of uneven parts 4 on both sides and a flat part 3' in the center. The space between the two film carriers 2, 2, these film carriers, and the spacer is maintained by the concave and convex portions 4 on both sides of the spacer 3 coming into close contact with each other, and the flat central portion 3' of the spacer 3 is film carrier 2,
Since it is not in contact with the semiconductor chip 5, no pressure is directly applied to the semiconductor chip from the spacer.
このような状態で電気検査、外観検査、出荷梱
包等の取扱い時にリールから他の空リールへ巻き
とる際の摩擦によつて生ずる静電気や、リール自
身の運搬時に起る振動の摩擦によつて生ずる静電
気は導電性スペーサの使用により発生することは
なくなり、かつスペーサによる圧力もなくなり、
従つてフイルムキヤリアにボンデイングされてい
る半導体チツプを破壊することなく取扱うことが
出来る特徴を有する。 In such conditions, static electricity is generated due to friction when winding from one reel to another empty reel during electrical inspection, visual inspection, shipping packaging, etc., and friction due to vibrations that occur when the reel itself is transported. Static electricity is no longer generated due to the use of conductive spacers, and the pressure caused by the spacers is also eliminated.
Therefore, it has the feature that the semiconductor chip bonded to the film carrier can be handled without destroying it.
以上はフイルムキヤリアをリールに巻いた場合
の実施例であるが、フイルムキヤリアを積み重ね
る場合などスペーサを必要とする全ての場合に適
用することが出来る。 Although the above is an example in which film carriers are wound on a reel, the present invention can be applied to any case where a spacer is required, such as when film carriers are stacked.
第１図は本発明の実施例で半導体チツプを搭載
したフイルムキヤリアを重ねる状態を示す斜視図
である。又、第２図Ａはフイルムキヤリアとスペ
ーサとの関係を詳細に示した側面図であり、第２
図Ｂはその上面図である。尚、図中
１……リール、２……フイルムキヤリア、３…
…スペーサ、４……凹凸加工部、５……半導体チ
ツプ、６……リード、３′……スペーサの中央部。
FIG. 1 is a perspective view showing a state in which film carriers on which semiconductor chips are mounted are stacked in accordance with an embodiment of the present invention. Furthermore, FIG. 2A is a side view showing the relationship between the film carrier and the spacer in detail.
Figure B is its top view. In addition, in the figure 1... reel, 2... film carrier, 3...
...Spacer, 4...Irregularized portion, 5...Semiconductor chip, 6...Lead, 3'...Center portion of spacer.
Claims (1)
うしを重なり合せる工程を有する半導体装置の製
造方法において、前記フイルムキヤリアが互いに
重なり合う部分の該フイルムキヤリア間に、両側
に凹凸加工部を有する導電性のスペーサを用いこ
の両側の凹凸加工部により前記半導体チツプに該
スペーサからの圧力が直接加わらないようにした
ことを特徴とする半導体装置の製造方法。1. In a method for manufacturing a semiconductor device, which includes a step of overlapping film carriers on which semiconductor chips are mounted, a conductive spacer having a concave-convex portion on both sides is used between the film carriers in the portion where the film carriers overlap each other. 1. A method of manufacturing a semiconductor device, characterized in that pressure from the spacer is not directly applied to the semiconductor chip by unevenly processed portions on both sides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14249179A JPS5666048A (en) | 1979-11-02 | 1979-11-02 | Device for making semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14249179A JPS5666048A (en) | 1979-11-02 | 1979-11-02 | Device for making semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5666048A JPS5666048A (en) | 1981-06-04 |
| JPS639657B2 true JPS639657B2 (en) | 1988-03-01 |
Family
ID=15316551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14249179A Granted JPS5666048A (en) | 1979-11-02 | 1979-11-02 | Device for making semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5666048A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555440U (en) * | 1991-12-27 | 1993-07-23 | 株式会社村田製作所 | Deflection yoke device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0497342U (en) * | 1991-01-17 | 1992-08-24 | ||
| CN111587614B (en) * | 2018-01-19 | 2021-09-10 | 株式会社富士 | Storage device and storage method with reel |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53142175A (en) * | 1977-05-17 | 1978-12-11 | Nec Corp | Storage structure for tape carrier containing semiconductor element |
-
1979
- 1979-11-02 JP JP14249179A patent/JPS5666048A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53142175A (en) * | 1977-05-17 | 1978-12-11 | Nec Corp | Storage structure for tape carrier containing semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555440U (en) * | 1991-12-27 | 1993-07-23 | 株式会社村田製作所 | Deflection yoke device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5666048A (en) | 1981-06-04 |
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