JPH0221654B2 - - Google Patents
Info
- Publication number
- JPH0221654B2 JPH0221654B2 JP57039550A JP3955082A JPH0221654B2 JP H0221654 B2 JPH0221654 B2 JP H0221654B2 JP 57039550 A JP57039550 A JP 57039550A JP 3955082 A JP3955082 A JP 3955082A JP H0221654 B2 JPH0221654 B2 JP H0221654B2
- Authority
- JP
- Japan
- Prior art keywords
- glass
- ceramic
- semiconductor element
- concavity
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000919 ceramic Substances 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000011521 glass Substances 0.000 claims abstract description 15
- 239000005394 sealing glass Substances 0.000 abstract description 7
- 239000008188 pellet Substances 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- 231100000989 no adverse effect Toxicity 0.000 abstract 1
- 238000007789 sealing Methods 0.000 description 14
- 239000002184 metal Substances 0.000 description 4
- 230000001771 impaired effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子を収納したセラミツクベー
スとセラミツクキヤツプとの接合面をガラス封止
するとともに、一端を前記半導体素子に電気的に
接続したリードの他端を前記接合面を通して外部
に導出する構成のガラス封止型半導体装置の改良
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is characterized in that a bonding surface between a ceramic base containing a semiconductor element and a ceramic cap is sealed with glass, and the other end of a lead having one end electrically connected to the semiconductor element is connected to the bonding surface. The present invention relates to an improvement in a glass-sealed semiconductor device having a configuration in which the semiconductor device is led out through the glass.
この種のガラス封止型半導体装置においては、
第１図ａのようにセラミツクベース１は半導体素
子を収納するための凹部２と、気密封止を実施す
る為のセラミツクキヤツプ３との接合部４とを有
している。５はリード、６はボンデイングワイ
ヤ、７は半導体素子である。 In this type of glass-sealed semiconductor device,
As shown in FIG. 1a, the ceramic base 1 has a recess 2 for accommodating a semiconductor element and a joint 4 with a ceramic cap 3 for hermetically sealing. 5 is a lead, 6 is a bonding wire, and 7 is a semiconductor element.
ここで大きな半導体素子を収納する場合は大き
な凹部を必要とするが、しかしながらセラミツク
ベースの外形寸法は一般にそのパツケージをプリ
ント基板等に実装する際の条件により規制をうけ
る為、凹部を大きくするためには封止接合部幅を
狭くすることにより達成させねばならない。 When storing a large semiconductor element, a large recess is required, but the external dimensions of the ceramic base are generally regulated by the conditions when mounting the package on a printed circuit board, etc., so it is necessary to make the recess large. must be achieved by narrowing the sealing joint width.
しかしながら、この種の構造の如く封止接合部
の狭い部分を有するパツケージ構造においては、
封止接合部の狭い部分での封止ガラスの保持量が
広い部品に比べ著しく少なくなり、封止ガラスの
絶対量不足を生じて気密性がそこなわれるという
問題が生じている。 However, in a package structure with a narrow portion of the sealing joint, such as this type of structure,
The amount of sealing glass held in the narrow part of the sealing joint is significantly smaller than that in the wider parts, resulting in an absolute shortage of sealing glass and a problem that airtightness is impaired.
したがつて、本発明の目的はキヤツプ部材のガ
ラス封着部の一部を素子載置部に向かつて突出さ
せることにより、これら従来技術の欠点を解消
し、大型ペレツトを収納する場合にも気密性の低
下等のないガラス封止型の半導体装置を提供する
ことにある。 Therefore, an object of the present invention is to eliminate these drawbacks of the prior art by making a part of the glass sealing part of the cap member protrude toward the element mounting part, and to achieve airtightness even when storing large pellets. It is an object of the present invention to provide a glass-sealed semiconductor device without deterioration in performance.
本発明の要旨は、第１のガラス保持可能領域を
有するセラミツクベースと、第２のガラス保持可
能領域を有するセラミツクキヤツプと、前記セラ
ミツクベースの第１の凹部内に固定された半導体
素子と、前記半導体素子からの電気信号をパツケ
ージ外へ導出するためのリードと、前記半導体素
子の電極パツドと前記リードとの間を接続するボ
ンデイングワイヤを有するガラス封止型半導体装
置において、前記セラミツクキヤツプは第２の凹
部を有し、前記第２の凹部への突出部を前記セラ
ミツクキヤツプに設け、かつ、前記突出部を設け
ることによつて前記第２のガラス保持可能領域の
面積を増大させ、前記第２のガラス保持可能領域
の面積は前記第１のガラス保持可能領域の面積よ
りも大となるように前記セラミツクキヤツプの形
状が規定されていることを特徴とするガラス封止
型半導体装置にある。 The gist of the present invention is to provide a ceramic base having a first glass-holding area, a ceramic cap having a second glass-holding area, a semiconductor element fixed in a first recess of the ceramic base, and a ceramic cap having a second glass-holding area. In a glass-sealed semiconductor device having a lead for leading an electrical signal from a semiconductor element to the outside of the package and a bonding wire for connecting an electrode pad of the semiconductor element and the lead, the ceramic cap is a second ceramic cap. a recessed portion, a protruding portion into the second recessed portion is provided on the ceramic cap, and the area of the second glass holding area is increased by providing the protruding portion; The glass-sealed semiconductor device is characterized in that the shape of the ceramic cap is defined such that the area of the first glass-holdable area is larger than the area of the first glass-holdable area.
以下、本発明を図面に示す例にしたがつて説明
する。 The present invention will be described below with reference to examples shown in the drawings.
第２図ａ，ｂは本発明による半導体装置の断面
図およびキヤツプの斜視図である。図示のよう
に、セラミツクベース１は半導体素子を収納する
為の凹部２が大型半導体素子を収納できるように
十分大きく成形されている。また、セラミツクキ
ヤツプ３も前記セラミツクベース１の凹部２と同
等またはそれ以上の大きさの凹部８を有してお
り、単にこのままでは封止接合部４の狭い部分に
おいては封止ガラスの不足が生じる。 2a and 2b are a sectional view and a perspective view of a cap of a semiconductor device according to the present invention. As shown in the figure, a ceramic base 1 is formed so that a recess 2 for accommodating a semiconductor element is sufficiently large to accommodate a large semiconductor element. Further, the ceramic cap 3 also has a recess 8 that is equal to or larger in size than the recess 2 of the ceramic base 1, and if left as is, there will be a shortage of sealing glass in the narrow part of the sealing joint 4. .
ところで、セラミツクキヤツプ３の凹部８は一
般に半導体素子７をセラミツクベース１に載置
し、その後所定の位置にワイヤボンデイングされ
たものにセラミツクキヤツプ３を封止ガラスによ
り封止した時に、セラミツクキヤツプ３低面が前
記ワイヤ６等に当つて半導体素子７の特性をそこ
なわない様にする為設けられている。そこで本発
明ではワイヤ等のない部分には凹部８を形成する
必要がないことに注目し、このワイヤ等に影響を
及ぼさない範囲で封止接合部４より凹部８への突
出部９を設け、これによりガラス保持可能領域を
実質的に増す構造とする。したがつて、凹部８の
有効性は失なわずに封止に必要なガラス量が確保
できる構造となり大型ペレツトの収納が可能とな
る。 Incidentally, the recess 8 of the ceramic cap 3 is generally formed when the semiconductor element 7 is placed on the ceramic base 1 and then the ceramic cap 3 is sealed with a sealing glass after wire bonding in a predetermined position. This is provided to prevent the surface from contacting the wire 6 and the like and damaging the characteristics of the semiconductor element 7. Therefore, in the present invention, attention is paid to the fact that it is not necessary to form the recess 8 in a portion where there is no wire, etc., and a protrusion 9 is provided from the sealing joint 4 to the recess 8 within a range that does not affect the wire, etc. This results in a structure that substantially increases the area in which glass can be held. Therefore, the structure is such that the amount of glass necessary for sealing can be secured without losing the effectiveness of the recess 8, and it is possible to store large pellets.
なお突出部９は両側から内方へ向かつて成形し
ているが、第３図のように両側のものを連結した
突出部９Ａとして構成してもよい。 Although the protrusions 9 are formed inwardly from both sides, they may be formed as protrusions 9A in which the protrusions on both sides are connected, as shown in FIG.
以上のように本発明の半導体装置によれば、セ
ラミツクキヤツプに突出部を設けてガラス封着部
の実質的面積の増大を図つているので、大型ペレ
ツトを収納するにもかかわらずパツケージの小型
化を図りかつ一方では封止性能の向上を達成する
ことができるという効果を奏する。 As described above, according to the semiconductor device of the present invention, the protrusion is provided on the ceramic cap to increase the substantial area of the glass sealing part, so the package can be made smaller even though it accommodates large pellets. At the same time, it is possible to achieve an improvement in sealing performance.
なお、本発明と類似した目的を持つ公知例とし
て、実公昭56−38768号公報がある。同公報によ
れば、金属細線を保護するとともに、シールパス
を最大限に長くするために、封着ガラスを二層と
している。すなわち、二層目のガラス層の幅をシ
ールパスの幅よりも狭く形成し、それによつて二
層目のガラス層側部近傍に空間を形成している。
この空間により金属細線が保護される。 Incidentally, as a publicly known example having a similar purpose to the present invention, there is Japanese Utility Model Publication No. 56-38768. According to the publication, two layers of sealing glass are used to protect the thin metal wire and to maximize the sealing path. That is, the width of the second glass layer is formed narrower than the width of the seal path, thereby forming a space near the side of the second glass layer.
This space protects the thin metal wire.
しかしながら、この考案によれば、二層目の封
着ガラス層を形成するためには前記シールパスの
幅はある程度大きくなければならない。シールパ
スが所定以上の幅を有さなければ、それより幅の
狭い二層目のガラス層は形成し得ないからであ
る。 However, according to this invention, in order to form the second sealing glass layer, the width of the sealing path must be large to some extent. This is because unless the seal path has a width equal to or greater than a predetermined width, a second glass layer having a narrower width cannot be formed.
本発明は、そのような問題点をも解決し得るも
のであり、同公報記載の考案者らが想定している
シールパスよりもさらに狭いシールパスを有する
半導体装置にも本発明を適用することができる。 The present invention can solve such problems, and can also be applied to semiconductor devices having a seal path that is narrower than the seal path envisioned by the inventors described in the publication. .
同公報記載の考案ではシールパスを狭くしない
で金属細線を保護することを前提としているのに
対し、本発明ではシールパスを狭くした場合でも
封止の完全性を保ち、かつ、金属細線を保護する
ことができる。従つて、前記考案に比しても大型
のペレツトを吸容できるという効果がある。 While the idea described in the same publication is based on the premise of protecting the thin metal wire without narrowing the seal path, the present invention maintains the integrity of the seal even when the seal path is narrowed, and protects the thin metal wire. Can be done. Therefore, compared to the above-mentioned invention, it has the advantage of being able to absorb large pellets.
第１図ａは従来の半導体装置の断面図、ｂはセ
ラミツクキヤツプの斜視図、第２図ａは本発明の
半導体装置の断面図、ｂはそのセラミツクキヤツ
プの斜視図、第３図は本発明の他の実施例を示す
セラミツクキヤツプの斜視図である。
１……セラミツクベース、２……凹部、３……
セラミツクキヤツプ、４……封止接合部（ガラス
封着部）、５……リード、６……ワイヤ、７……
半導体素子、８……凹部、９，９Ａ……突出部。
FIG. 1a is a sectional view of a conventional semiconductor device, b is a perspective view of a ceramic cap, FIG. 2a is a sectional view of a semiconductor device of the present invention, b is a perspective view of the ceramic cap, and FIG. 3 is a perspective view of the ceramic cap. FIG. 6 is a perspective view of a ceramic cap showing another embodiment of the present invention. 1...ceramic base, 2...recess, 3...
Ceramic cap, 4... Sealing joint (glass sealing part), 5... Lead, 6... Wire, 7...
Semiconductor element, 8... recess, 9, 9A... protrusion.
Claims (1)
クベースと、第２のガラス保持可能領域を有する
セラミツクキヤツプと、前記セラミツクベースの
第１の凹部内に固定された半導体素子と、前記半
導体素子からの電気信号をパツケージ外へ導出す
るためのリードと、前記半導体素子の電極パツド
と前記リードとの間を接続するボンデイングワイ
ヤを有するガラス封止型半導体装置において、前
記セラミツクキヤツプは第２の凹部を有し、前記
第２の凹部への突出部を前記セラミツクキヤツプ
に設け、かつ、前記突出部を設けることによつて
前記第２のガラス保持可能領域の面積を増大さ
せ、前記第２のガラス保持可能領域の面積は前記
第１のガラス保持可能領域の面積よりも大となる
ように前記セラミツクキヤツプの形状が規定され
ていることを特徴とするガラス封止型半導体装
置。 ２ 前記突出部は、前記第２の凹部を構成する辺
のうち、相対向する各々の辺から突出し、第１の
突出部と第２の突出部となるように形成されてい
ることを特徴とする特許請求の範囲第１項記載の
ガラス封止型半導体装置。 ３ 前記第１の突出部と前記第２の突出部とは連
結されていることを特徴とする特許請求の範囲第
２項記載のガラス封止型半導体装置。[Scope of Claims] 1. A ceramic base having a first glass-holding area, a ceramic cap having a second glass-holding area, and a semiconductor element fixed in a first recess of the ceramic base. In a glass-sealed semiconductor device having a lead for leading an electrical signal from the semiconductor element to the outside of the package and a bonding wire for connecting an electrode pad of the semiconductor element and the lead, the ceramic cap is 2 recesses, a protrusion into the second recess is provided on the ceramic cap, and by providing the protrusion, the area of the second glass holding area is increased; A glass-sealed semiconductor device, wherein the shape of the ceramic cap is defined such that the area of the second glass-holding area is larger than the area of the first glass-holding area. 2. The protrusion is formed so as to protrude from each opposing side of the sides constituting the second recess to form a first protrusion and a second protrusion. A glass-sealed semiconductor device according to claim 1. 3. The glass-sealed semiconductor device according to claim 2, wherein the first protrusion and the second protrusion are connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3955082A JPS58157152A (en) | 1982-03-15 | 1982-03-15 | Glass sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3955082A JPS58157152A (en) | 1982-03-15 | 1982-03-15 | Glass sealed type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58157152A JPS58157152A (en) | 1983-09-19 |
| JPH0221654B2 true JPH0221654B2 (en) | 1990-05-15 |
Family
ID=12556161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3955082A Granted JPS58157152A (en) | 1982-03-15 | 1982-03-15 | Glass sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58157152A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5773937U (en) * | 1980-10-24 | 1982-05-07 |
-
1982
- 1982-03-15 JP JP3955082A patent/JPS58157152A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58157152A (en) | 1983-09-19 |
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