JPS63262860A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS63262860A
JPS63262860A JP9843387A JP9843387A JPS63262860A JP S63262860 A JPS63262860 A JP S63262860A JP 9843387 A JP9843387 A JP 9843387A JP 9843387 A JP9843387 A JP 9843387A JP S63262860 A JPS63262860 A JP S63262860A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
circuit device
resin layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9843387A
Other languages
Japanese (ja)
Inventor
Tokuo Takeuchi
竹内 徳夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9843387A priority Critical patent/JPS63262860A/en
Publication of JPS63262860A publication Critical patent/JPS63262860A/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent the permeation of moisture, to stabilize the performance of a device and to improve reliability by forming a metallic molded form onto the surface of a semiconductor chip. CONSTITUTION:Semiconductor chips 2 loaded onto a substrate 1 are coated directly with surface protective resin layers 3, metallic molded-form layers 4 molded so as to include the resin layers 3 are fast stuck, and a resin layer 5 is applied so as to coat the whole hybrid integrated circuit device. Accordingly, the permeation of moisture is prevented by the layer 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装置、特に混成集積回路装置の保
護被覆の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and more particularly to the structure of a protective coating for a hybrid integrated circuit device.

〔従来の技術〕[Conventional technology]

“従来、この種の混成集積回路の保護被覆の構造は複数
層の樹脂により被覆するか、或いは最も外層に金属成形
体を被覆する構造となっていた。
``Conventionally, the structure of the protective coating for this type of hybrid integrated circuit was to cover it with multiple layers of resin, or to cover it with a metal molded body as the outermost layer.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の混成集積回路装置における前者の被覆構
造では、被覆層の樹脂による保護被覆を行った構造とな
っているので、一般に水分等の浸透が生じ、信頼性に乏
しく安価に高性能な混成集積回路装置を実現することが
できないという欠点がある。
The former covering structure in the conventional hybrid integrated circuit device described above has a structure in which a protective coating is made of resin as a coating layer, so moisture and other substances generally penetrate, resulting in poor reliability and low cost and high performance hybrid integrated circuit devices. The disadvantage is that an integrated circuit device cannot be realized.

また、後者のように最外層を金属成形体で覆う構造の保
護被覆では、金属成形体が大きくなりかつ混成集積回路
装置に内蔵される各種部品の異なる形状や高さに対し十
分な間隙をもって被覆されるよう金属成形体を加工する
必要があり、複雑な形状となるほど、安価に高性能な混
成集積回路装置を実現することができないという欠点を
有している。
In addition, in the latter case, where the outermost layer is covered with a metal molded body, the metal molded body is large, and the cover is covered with enough gaps to accommodate the different shapes and heights of the various components built into the hybrid integrated circuit device. It is necessary to process the metal molded body so that the shape of the metal body becomes more complex, and the more complicated the shape, the more difficult it is to realize a high-performance hybrid integrated circuit device at a low cost.

本発明の目的は水分等の浸透を阻止することにより信頼
性を高め、かつ安価な混成集積回路装置を提供すること
にある。
An object of the present invention is to provide a hybrid integrated circuit device that is highly reliable and inexpensive by preventing penetration of moisture and the like.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は回路を形成した基板上に複数個の半導体チップ
を搭載した混成集積回路装置において、半導体チップの
各々を別個に直接被覆する表面保護樹脂層と、該表面保
護樹脂層毎に該樹脂層を覆う金属成形体と、混成集積回
路装置全体を被覆する樹脂層とを有することを特徴とす
る混成集積回路装置である。
The present invention provides a hybrid integrated circuit device in which a plurality of semiconductor chips are mounted on a substrate on which a circuit is formed. This hybrid integrated circuit device is characterized by having a metal molded body that covers the hybrid integrated circuit device, and a resin layer that covers the entire hybrid integrated circuit device.

(実施例〕 次に本発明について図面を参照して説明する。(Example〕 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の構造を示す断面図である。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention.

第1図において、基板1上に搭載された半導体チップ2
の各々を個別に表面保護樹脂層3にて直接被覆する。樹
脂層3は、半導体の特性を劣化させるイオン性不純物を
排除するなど、一般に純度の高い半導体表面に直接被着
させることが可能な樹脂類を指し半導体チップや接続用
ワイヤーに対し機械的応力によるなどの損傷を与えない
ような特性を有する樹脂類による。
In FIG. 1, a semiconductor chip 2 mounted on a substrate 1
Each of these is individually directly coated with a surface protection resin layer 3. Resin layer 3 refers to a resin that can be applied directly to the surface of a generally high-purity semiconductor, such as by eliminating ionic impurities that degrade the characteristics of semiconductors, and is used to prevent mechanical stress on semiconductor chips and connecting wires. Made of resins with properties that do not cause damage, such as

さらに樹脂層3を包含するように成形された金属成形体
層4を密着させ、さらに混成集積回路装置全体を覆うよ
うに樹脂層5を被着させる。金属成形体層4は基板1の
導体を短絡させることのないように導体と接する部分に
切り欠きを設けるか或いは、通常よく用いられる構造の
ように基板1の回路導体上を酸化物膜など絶縁物で被覆
する必要があることは言うまでもない。
Further, a metal molded body layer 4 molded to include the resin layer 3 is brought into close contact with the resin layer 3, and a resin layer 5 is further applied so as to cover the entire hybrid integrated circuit device. The metal molded layer 4 is provided with a notch in the part that contacts the conductor so as not to short-circuit the conductor of the substrate 1, or an insulating film such as an oxide film is formed on the circuit conductor of the substrate 1 as in a commonly used structure. Needless to say, it is necessary to cover it with something.

このように構成された混成集積回路は金属成形体層4に
より水分の浸透が阻止され、半導体チップ2上の樹脂層
3を通してチップ2に水分が浸透することはなく、安定
な長期信頼性の実現が可能である。
In the hybrid integrated circuit configured in this way, moisture is prevented from penetrating by the metal molded body layer 4, and moisture does not penetrate into the chip 2 through the resin layer 3 on the semiconductor chip 2, achieving stable long-term reliability. is possible.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は基板上に複数個搭載された
半導体チップ上を直接被覆する表面保護樹脂層と、表面
保護樹脂層を覆う金属成形体層とさらに混成集積回路装
置全体を被覆する樹脂層とを有するため、金属成形体層
により半導体チップへの水分等の浸透を阻止でき、チッ
プの信頼性を長期間維持できる。さらに、金属成形体層
は、チップを直接被覆することはなく、予めチップ上を
被覆する樹脂層を覆うため、その形状を簡素化すること
でき、安価に高性能な混成集積回路装置を実現できると
いう効果を有するものである。
As explained above, the present invention includes a surface protection resin layer that directly covers a plurality of semiconductor chips mounted on a substrate, a metal molded body layer that covers the surface protection resin layer, and a resin that further covers the entire hybrid integrated circuit device. Since the metal molded body layer has a metal molded body layer, it is possible to prevent penetration of moisture and the like into the semiconductor chip, and the reliability of the chip can be maintained for a long period of time. Furthermore, since the metal molded body layer does not directly cover the chip, but covers the resin layer that covers the chip in advance, its shape can be simplified, and a high-performance hybrid integrated circuit device can be realized at low cost. This has the effect of

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例である混成集積回路装置の断
面図である。 1・・・基板        2・・・半導体チップ3
・・・表面保護樹脂層   4・・・金属成形体層5・
・・樹脂層
FIG. 1 is a sectional view of a hybrid integrated circuit device which is an embodiment of the present invention. 1...Substrate 2...Semiconductor chip 3
...Surface protection resin layer 4...Metal molded body layer 5.
・Resin layer

Claims (1)

【特許請求の範囲】[Claims] (1) 回路を形成した基板上に複数個の半導体チップ
を搭載した混成集積回路装置において、半導体チップの
各々を別個に直接被覆する表面保護樹脂層と、該表面保
護樹脂層毎に該樹脂層を覆う金属成形体と、混成集積回
路装置全体を被覆する樹脂層とを有することを特徴とす
る混成集積回路装置。
(1) In a hybrid integrated circuit device in which a plurality of semiconductor chips are mounted on a substrate on which a circuit is formed, a surface protection resin layer that directly covers each semiconductor chip separately, and a resin layer for each surface protection resin layer. 1. A hybrid integrated circuit device comprising: a metal molded body covering the hybrid integrated circuit device; and a resin layer covering the entire hybrid integrated circuit device.
JP9843387A 1987-04-21 1987-04-21 Hybrid integrated circuit device Pending JPS63262860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9843387A JPS63262860A (en) 1987-04-21 1987-04-21 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9843387A JPS63262860A (en) 1987-04-21 1987-04-21 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS63262860A true JPS63262860A (en) 1988-10-31

Family

ID=14219666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9843387A Pending JPS63262860A (en) 1987-04-21 1987-04-21 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS63262860A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600181A (en) * 1995-05-24 1997-02-04 Lockheed Martin Corporation Hermetically sealed high density multi-chip package
US5694300A (en) * 1996-04-01 1997-12-02 Northrop Grumman Corporation Electromagnetically channelized microwave integrated circuit
US8884424B2 (en) 2010-01-13 2014-11-11 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US9070793B2 (en) 2010-08-02 2015-06-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having electromagnetic interference shielding and related methods
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US9929078B2 (en) 2016-01-14 2018-03-27 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600181A (en) * 1995-05-24 1997-02-04 Lockheed Martin Corporation Hermetically sealed high density multi-chip package
US5694300A (en) * 1996-04-01 1997-12-02 Northrop Grumman Corporation Electromagnetically channelized microwave integrated circuit
US8884424B2 (en) 2010-01-13 2014-11-11 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US9196597B2 (en) 2010-01-13 2015-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US9070793B2 (en) 2010-08-02 2015-06-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having electromagnetic interference shielding and related methods
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US9929078B2 (en) 2016-01-14 2018-03-27 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

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