JPH05206361A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05206361A JPH05206361A JP4013916A JP1391692A JPH05206361A JP H05206361 A JPH05206361 A JP H05206361A JP 4013916 A JP4013916 A JP 4013916A JP 1391692 A JP1391692 A JP 1391692A JP H05206361 A JPH05206361 A JP H05206361A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead wire
- semiconductor
- adhesive portion
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置、特に、
半導体集積回路装置における半導体装置のリード線の半
田割れを防止し、積み重ね実装が可能な半導体装置に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to
The present invention relates to a semiconductor device in a semiconductor integrated circuit device, in which lead wires of the semiconductor device are prevented from cracking and solder can be stacked and mounted.
【０００２】[0002]
【従来の技術】図６は、従来の半導体装置例えばリード
線形状を有する半導体装置を示す側面図である。図にお
いて、半導体装置は、パッケージ部１とリード線２とを
備え、リード線２の先端は、半導体基板と接続される平
坦な接着部分３となっている。2. Description of the Related Art FIG. 6 is a side view showing a conventional semiconductor device, for example, a semiconductor device having a lead wire shape. In the figure, the semiconductor device includes a package portion 1 and a lead wire 2, and the tip of the lead wire 2 is a flat adhesive portion 3 connected to a semiconductor substrate.
【０００３】従来の半導体装置は上述したように構成さ
れ、上記のようなリード線形状を有する半導体装置から
なる半導体集積回路装置が大きな温度変化を伴う環境に
あると、半導体装置の熱膨張率と基板の熱膨張率との違
いから、大きな応力がリード線２と基板の半田接着部分
（図示しない）に加わる。その結果、半田割れが生じ、
信号線の接続不良となり、半導体集積回路装置が正常に
機能しなくなる。The conventional semiconductor device is configured as described above, and when the semiconductor integrated circuit device including the semiconductor device having the above-described lead wire shape is in an environment with a large temperature change, the coefficient of thermal expansion of the semiconductor device is Due to the difference from the thermal expansion coefficient of the board, a large stress is applied to the lead wire 2 and the solder-bonded portion (not shown) of the board. As a result, solder cracks occur,
The connection of the signal line becomes defective, and the semiconductor integrated circuit device does not function normally.
【０００４】また、超薄型のパッケージ、ＴＣＰ（Tape
Carrier Package）により、メモリＩＣの積み重ね実装
による集積密度向上の要求が高まっている。このような
状況のもと、半導体装置の積み重ねを容易にするリード
線の開発が急がれているが、具体的な形状を示したもの
は現在のところ見当たらない。In addition, an ultra-thin package, TCP (Tape
Carrier Packages) have increased the demand for higher integration density by stacking and mounting memory ICs. Under such circumstances, the development of lead wires for facilitating the stacking of semiconductor devices has been urgently pursued, but no one showing a specific shape has been found at present.
【０００５】[0005]
【発明が解決しようとする課題】上述したような半導体
装置では、半導体集積回路装置に大きな温度変化が繰り
返されると、半田接着部に大きな応力が加わり半田割れ
が生ずるという問題点があった。また、積み重ね実装を
必要とする場合にこれを可能とし、なおかつ上記半田割
れを防止するリード線の形状を具体的に示したものが見
当たらなかった。The semiconductor device as described above has a problem that when a large temperature change is repeated in the semiconductor integrated circuit device, a large stress is applied to the solder bonding portion to cause solder cracking. Further, it is not possible to find any one that specifically shows the shape of the lead wire that enables this when stacked mounting is required and that prevents the solder cracking.
【０００６】この発明は、このような問題点を解決する
ためになされたもので、半導体装置や基板に大きな温度
変化が生じ、熱膨張率の違いによって応力が半田接着部
に加わっても、リード線の弾力によって半田割れが生じ
ず、また、積み重ね実装が必要な場合にこれを可能とす
るリード線を備えた半導体装置を得ることを目的とす
る。The present invention has been made in order to solve such a problem, and even if a large temperature change occurs in a semiconductor device or a substrate and a stress is applied to a solder bonding portion due to a difference in coefficient of thermal expansion, a lead is formed. It is an object of the present invention to obtain a semiconductor device having a lead wire which does not cause solder cracking due to the elasticity of wires and which enables this when stacked mounting is required.
【０００７】[0007]
【課題を解決するための手段】この発明に係る半導体装
置は、複数個の半導体装置を互いに積み重ね実装できる
ように第１接着部及びこの第１接着部から上記パッケー
ジ部の厚さとほぼ等しい間隔で隔てられた第２接着部を
有し、かつ上記リード線は弾力保有部を有するように折
り曲げられているリード線を備えたものである。According to another aspect of the present invention, there is provided a semiconductor device in which a plurality of semiconductor devices can be stacked and mounted on each other at a first adhesive portion and at an interval from the first adhesive portion which is approximately equal to a thickness of the package portion. The lead wire has a second adhesive portion that is separated, and the lead wire includes a lead wire that is bent so as to have an elasticity retaining portion.
【０００８】[0008]
【作用】この発明においては、リード線の第１接着部及
び第２接着部によって複数個の半導体装置の積み重ね実
装を行うことができ、かつリード線の弾力保有部によっ
て熱膨張等による応力を吸収、緩和し、半田接着部の半
田割れを防止する。According to the present invention, a plurality of semiconductor devices can be stacked and mounted by the first bonding portion and the second bonding portion of the lead wire, and the elastic holding portion of the lead wire absorbs stress due to thermal expansion or the like. , Mitigates and prevents solder cracks at solder joints.
【０００９】[0009]
【実施例】図１は、この発明の一実施例による半導体装
置を示す側面図である。なお、各図中、同一符号は同一
又は相当部分を示している。図において、半導体装置
は、半導体素子（図示しない）を樹脂封止したパッケー
ジ部１と、リード線２Ａとを備えている。このリード線
２Ａには、半導体基板と接続され、又は複数個の半導体
装置を積層する際に半田付けされる第１接着部３Ａ及び
第２接着部３Ｂが設けられている。また、リード線２Ａ
はＺ形の形状をしており、リード線２Ａの端部は左右で
同じ側に位置している。なお、上記第１接着部３Ａと第
２接着部３Ｂとの間隔は、パッケージ部１の厚さとほぼ
等しくしておく。1 is a side view showing a semiconductor device according to an embodiment of the present invention. In each drawing, the same reference numerals indicate the same or corresponding parts. In the figure, the semiconductor device includes a package portion 1 in which a semiconductor element (not shown) is sealed with a resin, and a lead wire 2A. The lead wire 2A is provided with a first adhesive portion 3A and a second adhesive portion 3B which are connected to a semiconductor substrate or soldered when laminating a plurality of semiconductor devices. Also, the lead wire 2A
Has a Z shape, and the ends of the lead wire 2A are located on the same side on the left and right. The distance between the first adhesive portion 3A and the second adhesive portion 3B is set to be substantially equal to the thickness of the package portion 1.
【００１０】上述したように構成された半導体装置にお
いて、第２接着部３Ｂは、リード線に弾力を持たせるた
めの弾力保有部となる。すなわち、半導体装置が基板に
実装された後、外力や熱膨張による応力が加わると、パ
ッケージ部１に対する第１接着部３Ａの相対的位置が変
化する。従来は、この応力が半田に加わり半田割れを生
じていたが、第２接着部３Ｂが弾力保有部としてこの変
位を吸収、緩和するので、半田に無理な力が加わらな
い。その結果、半田割れを防止でき、接続不良を防止で
きる。同時に、第１接着部３Ａと第２接着部３Ｂとの間
隔は、パッケージ部１の厚さとほぼ等しいので、これら
第１接着部３Ａ及び第２接着部３Ｂにより半導体装置を
互いに積み重ね実装することができる。In the semiconductor device configured as described above, the second adhesive portion 3B serves as an elasticity holding portion for giving elasticity to the lead wire. That is, after the semiconductor device is mounted on the substrate, when the external force or the stress due to the thermal expansion is applied, the relative position of the first adhesive portion 3A with respect to the package portion 1 changes. Conventionally, this stress was applied to the solder to cause solder cracking, but since the second adhesive portion 3B functions as an elastic holding portion to absorb and relax this displacement, an unreasonable force is not applied to the solder. As a result, solder cracking can be prevented and connection failure can be prevented. At the same time, since the distance between the first adhesive portion 3A and the second adhesive portion 3B is substantially equal to the thickness of the package portion 1, the semiconductor devices can be stacked and mounted on each other by the first adhesive portion 3A and the second adhesive portion 3B. it can.
【００１１】図２は、図１に示した半導体装置における
リード線２Ａの形状を、その一方の側を反転するように
変形したものである。従って、リード線２Ａの端部は、
互いに異なる側に位置している。図１の半導体装置で
は、メモリＩＣなどのように裏向きで実装する必要のあ
る場合、半田割れ防止の効果が十分でない場合がある
が、図２に示すように、第１接着部３Ａ及び第２接着部
３Ｂを左右で反転することにより、メモリＩＣの場合に
も裏向きでもそのまま実装することができ、上述のよう
な熱膨張による半田割れを表向きに実装した時と同様に
防止できる。FIG. 2 shows a modification of the lead wire 2A in the semiconductor device shown in FIG. 1 so that one side thereof is inverted. Therefore, the end of the lead wire 2A is
They are located on different sides. In the semiconductor device of FIG. 1, when it is necessary to mount the semiconductor device face down like a memory IC, the effect of preventing solder cracking may not be sufficient, but as shown in FIG. By inverting the two adhesive portions 3B from side to side, the memory IC can be mounted as it is even when it is face down, and it is possible to prevent the solder crack due to the thermal expansion as described above from being mounted face up.
【００１２】図３は、リード線２Ｂの形状をループ状
（Ｃ形状）にした半導体装置を示している。この場合、
第２接着部３Ｄが弾力保有部となり、上述と同様な半田
割れを防止する効果を奏する。また、リード線２Ｂの端
部は、左右で同じ側に位置している。さらに、第１接着
部３Ｃ及び第２接着部３Ｄにより、半導体装置同士を互
いに積み重ね実装することが可能である。FIG. 3 shows a semiconductor device in which the lead wire 2B has a loop shape (C shape). in this case,
The second adhesive portion 3D serves as an elasticity retaining portion, and has the same effect of preventing solder cracks as described above. The ends of the lead wires 2B are located on the same side on the left and right. Further, the first adhesive portion 3C and the second adhesive portion 3D allow the semiconductor devices to be stacked and mounted on each other.
【００１３】図４は、図３に示した半導体装置における
左右一方のリード線２Ｂの第１接着部３Ｃと第２接着部
３Ｄとを反転したものであり、リード線２Ｂの端部は、
互いに異なる側に位置している。この場合も、上述した
図２の場合と同様に、裏向きでもそのまま実装すること
ができる。FIG. 4 is a diagram in which the first bonding portion 3C and the second bonding portion 3D of the left and right lead wires 2B in the semiconductor device shown in FIG. 3 are reversed, and the ends of the lead wires 2B are
They are located on different sides. In this case as well, as in the case of FIG. 2 described above, the device can be mounted as it is even if it is face down.
【００１４】図５は、図４に示した半導体装置を多段に
（図５では３段に）積み重ね実装した状態を示してい
る。このような積み重ね実装においても、上述と同様に
半田割れを防止することができる。なお、リード線の形
状は、第１接着部３Ｃと第２接着部３Ｄが左右で反転し
ていても又は同じ側にあってもよい。FIG. 5 shows a state in which the semiconductor devices shown in FIG. 4 are stacked and mounted in multiple stages (three stages in FIG. 5). Even in such stacking mounting, solder cracking can be prevented as described above. The shape of the lead wire may be such that the first adhesive portion 3C and the second adhesive portion 3D are laterally reversed or on the same side.
【００１５】[0015]
【発明の効果】この発明は以上説明したとおり、半導体
素子を樹脂封止したパッケージ部と、このパッケージ部
の側部から突出したリード線とを備えた半導体装置であ
って、上記リード線は、第１接着部及びこの第１接着部
から上記パッケージ部の厚さとほぼ等しい間隔で隔てら
れた第２接着部を有し、かつ弾力保有部を有するように
折り曲げられているので、外部から若しくは熱膨張によ
る応力に対して弾力保有部がこれを吸収、緩和し半田接
着部に直接大きな応力が加わらないので、半田割れを防
止でき、熱サイクルに対する信頼性を飛躍的に向上させ
ることができると共に、多段の積み重ね実装や裏向き実
装も行うことができるという効果を奏する。As described above, the present invention is a semiconductor device including a package portion in which a semiconductor element is sealed with a resin, and a lead wire protruding from a side portion of the package portion, wherein the lead wire comprises: Since it has a first adhesive portion and a second adhesive portion that is separated from the first adhesive portion by a distance substantially equal to the thickness of the package portion, and is bent so as to have an elastic holding portion, it is external or heat The elasticity holding part absorbs and relaxes the stress due to expansion and a large stress is not directly applied to the solder bonding part, so solder cracking can be prevented and the reliability against heat cycle can be dramatically improved. It is possible to perform multi-level stacking mounting and face-down mounting.
【図１】この発明の一実施例による半導体装置を示す側
面図である。FIG. 1 is a side view showing a semiconductor device according to an embodiment of the present invention.
【図２】この発明の他の実施例による半導体装置を示す
側面図である。FIG. 2 is a side view showing a semiconductor device according to another embodiment of the present invention.
【図３】この発明のさらに他の実施例による半導体装置
を示す側面図である。FIG. 3 is a side view showing a semiconductor device according to still another embodiment of the present invention.
【図４】この発明のさらに他の実施例による半導体装置
を示す側面図である。FIG. 4 is a side view showing a semiconductor device according to still another embodiment of the present invention.
【図５】図４に示した半導体装置を多段に積み重ね実装
した状態を示す側面図である。FIG. 5 is a side view showing a state in which the semiconductor devices shown in FIG. 4 are stacked and mounted in multiple stages.
【図６】従来の半導体装置を示す側面図である。FIG. 6 is a side view showing a conventional semiconductor device.
１ パッケージ部 ２Ａ、２Ｂ リード線 ３Ａ、３Ｃ 第１接着部 ３Ｂ、３Ｄ 第２接着部 1 Package Part 2A, 2B Lead Wires 3A, 3C First Adhesive Part 3B, 3D Second Adhesive Part
Claims (1)
と、このパッケージ部の側部から突出したリード線とを
備えた半導体装置であって、 上記リード線は、第１接着部及びこの第１接着部から上
記パッケージ部の厚さとほぼ等しい間隔で隔てられた第
２接着部を有し、かつ弾力保有部を有するように折り曲
げられていることを特徴とする半導体装置。1. A semiconductor device comprising a package portion in which a semiconductor element is sealed with a resin, and a lead wire protruding from a side portion of the package portion, wherein the lead wire includes a first adhesive portion and a first adhesive portion. A semiconductor device having a second adhesive portion separated from the adhesive portion at a distance substantially equal to the thickness of the package portion, and being bent so as to have an elastic holding portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4013916A JPH05206361A (en) | 1992-01-29 | 1992-01-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4013916A JPH05206361A (en) | 1992-01-29 | 1992-01-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05206361A true JPH05206361A (en) | 1993-08-13 |
Family
ID=11846497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4013916A Pending JPH05206361A (en) | 1992-01-29 | 1992-01-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05206361A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114759A (en) * | 1998-04-23 | 2000-09-05 | Nec Corporation | Semiconductor package |
| KR100671268B1 (en) * | 2005-08-08 | 2007-01-19 | 삼성전자주식회사 | Semiconductor package having z-shaped outer leads and package stack structure and method using the same |
| US9515013B2 (en) | 2014-09-12 | 2016-12-06 | Kabushiki Kaisha Toshiba | Semiconductor device |
-
1992
- 1992-01-29 JP JP4013916A patent/JPH05206361A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114759A (en) * | 1998-04-23 | 2000-09-05 | Nec Corporation | Semiconductor package |
| KR100671268B1 (en) * | 2005-08-08 | 2007-01-19 | 삼성전자주식회사 | Semiconductor package having z-shaped outer leads and package stack structure and method using the same |
| US9515013B2 (en) | 2014-09-12 | 2016-12-06 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US9620442B2 (en) | 2014-09-12 | 2017-04-11 | Kabushiki Kaisha Toshiba | Semiconductor device |
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