JPH01191455A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01191455A JPH01191455A JP1445188A JP1445188A JPH01191455A JP H01191455 A JPH01191455 A JP H01191455A JP 1445188 A JP1445188 A JP 1445188A JP 1445188 A JP1445188 A JP 1445188A JP H01191455 A JPH01191455 A JP H01191455A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- hole
- leads
- package
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims description 4
- 239000008188 pellet Substances 0.000 claims description 4
- 238000005452 bending Methods 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 241000233780 Scilla Species 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特にレジンモールド型の半導体
装置に適用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective when applied to semiconductor devices, particularly resin molded semiconductor devices.
ＤＩＰ（ドユアルインラインパッケージ）型の半導体装
ｆＩｔ（ＩＣ）については特開昭５８−２７３４８号公
報等で開示されている。その概要は、半導体ペレットを
載置しているタブと、その近傍まで一端を延在させ、前
記ペレット上の電極とボンディングワイヤを介して電気
的に接続しており、他端がレジンパッケージの対向する
両側面から突出して形成されているリードを有している
ものである。A DIP (dual in line package) type semiconductor device fIt (IC) is disclosed in Japanese Patent Laid-Open No. 58-27348 and the like. The outline is that one end extends to the tab on which the semiconductor pellet is placed, one end extends to the vicinity thereof, and is electrically connected to the electrode on the pellet via a bonding wire, and the other end faces the resin package. It has leads that are formed to protrude from both sides of the device.
ところが、このような半導体装置（以下単にＩＣという
）ではリードがレジンパッケージから突出しているため
、次のような問題がある。（１）搬送。However, in such a semiconductor device (hereinafter simply referred to as an IC), the leads protrude from the resin package, which causes the following problems. (1) Transportation.
測定中に外的要因により屈曲してしまう場合がある。そ
のため、屈曲したリードの修正作業が必要となり多大な
時間を要する。また、屈曲したす＋ドからメツキが落ち
る不良が生じる等の問題が発生し易い。さらに、完全に
折れ曲がり修正不可能なＩＣは不良品として処分される
ことになる。（２）リードが外部に接触し易いため静電
破壊を起こし一不良品にしてしまう危険性が高い。During measurement, it may be bent due to external factors. Therefore, it is necessary to correct the bent lead, which takes a lot of time. Further, problems such as defects in which the plating falls off from bent doors are likely to occur. Furthermore, ICs that are completely bent and cannot be corrected are disposed of as defective products. (2) Since the leads easily come into contact with the outside, there is a high risk of electrostatic damage resulting in a defective product.
本発明の目的は、レジンパッケージから突出したリード
（アウターリード）に起因する不良を根本から解決する
ことにある。An object of the present invention is to fundamentally solve defects caused by leads (outer leads) protruding from a resin package.
本発明の前記ならびＫそのほかの目的と新規な特徴は、
本明細書の記述及び添付図面からあきらかになるであろ
う。The above and other objects and novel features of the present invention are:
It will become clear from the description of this specification and the accompanying drawings.
本Ｈにおいて開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in Book H is as follows.
すなわち、パッケージからリードを突出させることなく
埋設した状態にし、各埋設したり−ドに連通する孔を設
けるものである。That is, the leads are buried without protruding from the package, and holes communicating with each buried lead are provided.
上記した手段によれば、リード曲がり及びＩＪ −ド接
触忙よる静電破壊を完全に防止できるものである。According to the above-mentioned means, it is possible to completely prevent lead bending and electrostatic damage caused by IJ-domain contact.
〔実施例１〕
第１図は本発明の一実施例であるＩＣの断面図、第２図
は第１図で示すＩＣの全体構成図である。[Embodiment 1] FIG. 1 is a sectional view of an IC that is an embodiment of the present invention, and FIG. 2 is an overall configuration diagram of the IC shown in FIG. 1.
以下、図面に従い説明する。ｌは半導体チップでありそ
の主表面上には電極（図示せず）が形成されている。２
は半導体チップｌを搭載するためのタブであり、その周
囲には一端がタブ近傍にまで近接し、他端はレジンパッ
ケージ３から突出することなく埋設したままとなってい
るリード４が複数本形成されている。５は前記リード４
の少なくともどちらか一方の表面まで連通ずるスルーホ
ールであり、各々リードに対応して設けられている。６
は前記スルーホール５に対応してリード４に設けられた
ホールであり、例えば実装基板側に設けられた外部コン
タクトとしてのピンの先端を前記ホールに挿入して接続
できるようになっている。なお、７は半導体チップ１の
電極とり−ド４とを電気的に接続するボンディングワイ
ヤである。The explanation will be given below according to the drawings. 1 is a semiconductor chip, and an electrode (not shown) is formed on the main surface thereof. 2
is a tab for mounting a semiconductor chip l, around which a plurality of leads 4 are formed, one end of which is close to the vicinity of the tab, and the other end of which remains buried without protruding from the resin package 3. has been done. 5 is the lead 4
This is a through hole that communicates with at least one surface of the lead, and is provided corresponding to each lead. 6
is a hole provided in the lead 4 corresponding to the through hole 5, and for example, the tip of a pin as an external contact provided on the mounting board side can be inserted into the hole for connection. Note that 7 is a bonding wire that electrically connects the electrode lead 4 of the semiconductor chip 1.
〔実施例２〕
第３図は本発明の他の実施例であるＩＣの断面図である
。〔実施例１〕と同一構成部分については同一符号を付
し、その説明は省略する。図示するように、本実施例で
はタブ２に比較してリード８を下げるととＫより各リー
ド８に連通する孔９の長さＨが短くなるようにしている
。このようなＩＣにおいては、図示するように孔９に対
応して。[Embodiment 2] FIG. 3 is a sectional view of an IC that is another embodiment of the present invention. Components that are the same as those in [Embodiment 1] are designated by the same reference numerals, and their explanations will be omitted. As shown in the figure, in this embodiment, when the leads 8 are lowered compared to the tabs 2, the length H of the hole 9 communicating with each lead 8 becomes shorter than K. In such an IC, the hole 9 corresponds to the hole 9 as shown in the figure.
実装基板１０側にリード８と接続する半田バンプ１１な
どを形成しておくことにより、リフローソルダリング技
術などを用いて容易に実装することが可能となる。なお
、１２は配線層、１３は前記配線層１２上に薄膜したソ
ルダーレジストである。By forming solder bumps 11 and the like to be connected to the leads 8 on the mounting board 10 side, it becomes possible to easily mount using reflow soldering technology or the like. Note that 12 is a wiring layer, and 13 is a solder resist thin film formed on the wiring layer 12.
次に、本実施例から得られる作用・効果について記載す
る。Next, the actions and effects obtained from this example will be described.
（１） リードをパッケージ内圧内在させ、かつ外部
コンタクトと接触できるように各リードに連通する孔を
形成することにより、パッケージの外面に突起物となる
リードが形成されないので、ＩＣを搬送している際、あ
るいはハンドリング中などにおいて外部と接触してリー
ド曲がりが発生するという問題を解決できるという効果
が得られるものである。(1) By making the leads internal to the internal pressure of the package and by forming holes that communicate with each lead so that they can come into contact with external contacts, the leads that become protrusions are not formed on the outer surface of the package, making it easier to transport the IC. This has the effect of solving the problem of bending of the lead due to contact with the outside during handling or handling.
（２） 前記孔をリードの両面に形成させることによ
り、導電性のピンを挿入するだけでＩＣの重ね合わせが
容易に可能となり、ＩＣの機能アップが容易に行なえる
という効果が得られる。(2) By forming the holes on both sides of the lead, ICs can be easily stacked together simply by inserting conductive pins, and the functionality of the ICs can be easily improved.
（３） リードをパッケージ内に内在させ、かつ外部
コンタクトと接触できるように各リードに連通ずる孔を
形成することにより、パッケージの外面忙突起物となる
リードが形成されないので、リード接触に起因する静電
破壊を防止できるという効果が得られる。(3) By making the leads internal to the package and by forming a hole that communicates with each lead so that they can contact external contacts, the leads that become protrusions on the outside of the package are not formed, so there is no need to worry about lead contact. This has the effect of preventing electrostatic damage.
（４） リードをパッケージの表裏一方何に近接させ
て配置し、かつリードに近いパッケージの面からり−ド
に連通する孔を形成することにより、孔を短く形成でき
るので、実装基板側に半田バンプを形成して実装できる
という効果が得られる。(4) By arranging the leads close to either the front or back of the package, and by forming holes that communicate with the leads from the surface of the package near the leads, the holes can be formed short, making it possible to avoid soldering on the mounting board side. The effect is that bumps can be formed and mounted.
（５）パッケージからリードが突出して形成されていな
いので、極めて高密度な実装が可能となるという効果が
得られるものである。(5) Since the leads are not formed to protrude from the package, it is possible to achieve the effect that extremely high-density packaging is possible.
以上本発明によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種、々変更可
能であることはいうまでもない。たとえば、第４図に示
すように孔１４内にリード１５と接続する弾性導電体１
６が埋設されていても良い。Although the invention made by the present invention has been specifically explained above based on examples, it is to be understood that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Not even. For example, as shown in FIG. 4, an elastic conductor 1 connected to a lead 15 in a hole 14
6 may be buried.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、実装密度向上、リード曲がり防止及びリード
接触に起因する静電破壊防止を達成できるものである。That is, it is possible to improve the packaging density, prevent lead bending, and prevent electrostatic damage caused by lead contact.
第１図は本発明の一実施例である半導体装置の断面図。
第２図は第１図で示した半導体装置の全体構成図、
第３図、第４図は本発明の他の実施例を示す断面図であ
る。
１・・・半導体チップ、２・・・タブ、３・・・パッケ
ージ。
４．８．１５・・・リード、５．９．１４・・・孔、６
・・・ホール、７・・・ボンディングワイヤ、１０・・
・実装基板、１１・・・半田バンブ、１２・・・配線層
、１３・・・ソルダーレジスト、１６・・・弾性導電体
。
第 １ 図
第２図
丙
Ｊ？−へ′１〜ソデー〉１１
４−リーＹ・′
６−孔
Ｃ−が−ル
アー爪゛′シラ第７； ７＝’イマ
第 ３ 図
第４図
／FIG. 1 is a sectional view of a semiconductor device that is an embodiment of the present invention. FIG. 2 is an overall configuration diagram of the semiconductor device shown in FIG. 1, and FIGS. 3 and 4 are sectional views showing other embodiments of the present invention. 1... Semiconductor chip, 2... Tab, 3... Package. 4.8.15... Lead, 5.9.14... Hole, 6
...Hole, 7...Bonding wire, 10...
- Mounting board, 11... Solder bump, 12... Wiring layer, 13... Solder resist, 16... Elastic conductor. Figure 1 Figure 2 C?J? -To'1~Sode>11 4-Lee Y・' 6-Hole C- is -Lure claw 'Scilla No. 7; 7='Ima No. 3 Figure Figure 4/
Claims (1)
までその一端を延在せしめているリードと、前記リード
とペレット上の電極とを接続するワイヤと、それらを一
体に封止するレジンパッケージを有する半導体装置にお
いて、前記パッケージ外部からその対応するリードまで
連通する孔がリード延在方向に対して垂直に設けられて
いることを特徴とする半導体装置。 ２、前記孔はレジンパッケージの表面及び裏面両方に形
成されていることを特徴とする特許請求の範囲第１項記
載の半導体装置。 ３、前記孔にはリードと接続した導電材料が埋設されて
いることを特徴とする特許請求の範囲第１項記載の半導
体装置。 ４、前記導電材料は弾性を有することを特徴とする特許
請求の範囲第３項記載の半導体装置。[Claims] 1. A tab on which a semiconductor pellet is placed, a lead whose one end extends to the vicinity of the tab, a wire connecting the lead and an electrode on the pellet, and a combination thereof. 1. A semiconductor device having a resin package sealed in a resin package, wherein a hole communicating from the outside of the package to its corresponding lead is provided perpendicularly to the direction in which the lead extends. 2. The semiconductor device according to claim 1, wherein the hole is formed on both the front and back surfaces of the resin package. 3. The semiconductor device according to claim 1, wherein a conductive material connected to a lead is buried in the hole. 4. The semiconductor device according to claim 3, wherein the conductive material has elasticity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1445188A JPH01191455A (en) | 1988-01-27 | 1988-01-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1445188A JPH01191455A (en) | 1988-01-27 | 1988-01-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01191455A true JPH01191455A (en) | 1989-08-01 |
Family
ID=11861401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1445188A Pending JPH01191455A (en) | 1988-01-27 | 1988-01-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01191455A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06163744A (en) * | 1992-11-27 | 1994-06-10 | Nec Corp | Ic package and printed board |
| JPH06268101A (en) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate |
| US5856212A (en) * | 1994-05-11 | 1999-01-05 | Goldstar Electron Co., Ltd. | Method of producing semiconductor package having solder balls |
| JP2003100945A (en) * | 2001-09-27 | 2003-04-04 | Fujitsu Ltd | Semiconductor device, and semiconductor device unit and manufacturing method thereof |
| JP2005531925A (en) * | 2002-06-28 | 2005-10-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Wearable silicon chip |
| JP2009105334A (en) * | 2007-10-25 | 2009-05-14 | Spansion Llc | Semiconductor device and manufacturing method therefor |
| US8502385B2 (en) | 2010-10-20 | 2013-08-06 | Mitsubishi Electric Corporation | Power semiconductor device |
| JP2013152966A (en) * | 2012-01-24 | 2013-08-08 | Mitsubishi Electric Corp | Power semiconductor device, and method of manufacturing the same |
-
1988
- 1988-01-27 JP JP1445188A patent/JPH01191455A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06163744A (en) * | 1992-11-27 | 1994-06-10 | Nec Corp | Ic package and printed board |
| JPH06268101A (en) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate |
| US5856212A (en) * | 1994-05-11 | 1999-01-05 | Goldstar Electron Co., Ltd. | Method of producing semiconductor package having solder balls |
| JP2003100945A (en) * | 2001-09-27 | 2003-04-04 | Fujitsu Ltd | Semiconductor device, and semiconductor device unit and manufacturing method thereof |
| JP4695796B2 (en) * | 2001-09-27 | 2011-06-08 | 富士通セミコンダクター株式会社 | Semiconductor device, semiconductor device unit and manufacturing method thereof |
| JP2005531925A (en) * | 2002-06-28 | 2005-10-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Wearable silicon chip |
| JP4704749B2 (en) * | 2002-06-28 | 2011-06-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Wearable silicon chip |
| JP2009105334A (en) * | 2007-10-25 | 2009-05-14 | Spansion Llc | Semiconductor device and manufacturing method therefor |
| US8421241B2 (en) | 2007-10-25 | 2013-04-16 | Spansion Llc | System and method for stacking a plurality of electrically coupled semiconductor chips with a conductive pin |
| US9397025B2 (en) | 2007-10-25 | 2016-07-19 | Cypress Semiconductor Corporation | Semiconductor device and method for manufacturing thereof |
| US8502385B2 (en) | 2010-10-20 | 2013-08-06 | Mitsubishi Electric Corporation | Power semiconductor device |
| JP2013152966A (en) * | 2012-01-24 | 2013-08-08 | Mitsubishi Electric Corp | Power semiconductor device, and method of manufacturing the same |
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