JPS6394684A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make an epitaxial Si layer and a poly Si layer smoothly and continuously grow on a Si substrate's exposed surface and on an insulating film, respectively, without broken layers so that a good continuity state can be obtained, by performing vapor epitaxial growth of Si on a silicon substrate on which an insulating film is selectively formed under a reduced-pressure flow of a growth gas which is formed by mixing a silane group silicon source gas into a carrier gas comprising hydrogen. CONSTITUTION:A field silicon dioxide (SiO2) film 2 is formed so as to separate/ expose an element formation region DA on a surface of a p-type Si substrate 1 by a selective oxidation method and concurrently a p-type channel stopper 3 is formed. Vapor growth of a Si layer is performed under a reduced-pressure flow of a growth gas which is formed by mixing a silane group gas as a Si source into a H2 carrier gas. An epitaxial Si layer ES and a poly Si layer PS are smoothly and continuously formed on the exposed element formation region DA of the Si substrate 1 and on the field SiO2 film 2, respectively, without an broken layer. Then, boron (B) of desired concentration is introduced to provide p-type continuity for the epitaxial Si layer ES and the poly Si layer PS.

Description

[Detailed Description of the Invention] [Summary] An epitaxial Si layer is grown in vapor phase on a silicon (Si) substrate, and a polycrystalline St (poly-sDN) layer is simultaneously grown in vapor phase on an insulating film on the Si substrate. The epitaxial S layer on the Si5 plate is grown by using a silane-based Si source gas and a hydrogen (H2) carrier gas under reduced pressure to form a smooth continuous layer.
ii PolyS on the insulating film with good electrical connection with the electrical layer
i Obtain a conductive layer.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of simultaneously forming an epitaxial Si layer on a semiconductor substrate and a poly layer 511g on an insulating film in a smooth continuous state.

In MO3 type semiconductor integrated circuit devices (MOS IC), an elevated source/drain (el
An evalated-S/D) structure is used.

Furthermore, in bipolar ICs, a po'JSi base electrode lead structure is used in order to reduce the junction capacitance of the base region and increase the speed.

FIG. 4 is a schematic side sectional view showing the elevated source/drain structure, in which 51 is a p-type silicon substrate, 52 is a field insulating film, 53 is a p-type channel forming region, 54 is a gate insulating film, 55 is a gate electrode, 56 is an n' source region, 57 is an n' source pulling region, 5
Reference numeral 8 indicates an n-type drain region 59, an n4-type drain pull-up region, ES an epitaxial Si layer, and ps a poly-Si layer.

Further, FIG. 5 is a schematic side sectional view showing the above-mentioned base electrode extraction structure, in which 51 is a p-type silicon substrate, 52 is a
is a field insulating film, 60 is an n'' buried (n''b) layer, 61 is an n-type collector region, 62 is a p-type base region,
63 is a p-type base extraction electrode, 64 is an insulating film, and 65 is an n-type base electrode.
゛゛Emitter region, ES is epitaxial Sil''!
PS indicates a poly-Si layer.

When forming such a structure, an epitaxial S layer is formed on the back side of the St-based substrate 51 in which the channel formation region 53, source region 56, drain region 58, base region 62, etc. are formed.
The i-layer ES and the poly 5iJiWps formed on the field insulating film 52 and in which the source pull-up region 57, drain pull-up region 59, base extraction electrode 63, etc. are formed are simultaneously formed by vapor phase growth means. A source pull-up region 57 where a fault is likely to occur between the epitaxial 5iFiJES and the poly 31 layer psO and where wiring is connected;
There is a problem in that the electrical connections between the drain pull-up region 59, the base extraction electrode 63, etc. and the source region 56, the drain region 58, the base region 62, etc. become incomplete, and the performance of the semiconductor device is impaired.

Therefore, an epitaxial Si layer (
ES) and a poly-Si layer (P) grown on the field insulating film.
There is a need for a technology to form S) smoothly and continuously without any faults.

[Conventional technology]

The above epitaxial Si layer (ES) and poly-Si layer (PS)
) has conventionally been carried out by atmospheric vapor phase growth using a silane-based gas as a source gas and hydrogen as a carrier gas.

Typical growth conditions include monosilane (SiH4) flow rate of 50cc/min, hydrogen (n
2) Carrier gas flow i1 11/min Growth gas pressure Normal pressure growth temperature 950 to 1050°C.

However, according to the above conventional method, as shown in FIG.
A fault C1 occurs at the interface (transition plane) between iJiES and the poly-Si layer ps grown simultaneously on the field insulating film 52.
In addition, the poly-Si layer (PS) grown on the insulating film also grows in granular form as shown in the figure, causing extreme unevenness and cut-off Fcz in the poly-Si layer (PS). Mi of the elevated source-drain structure is easily
s) A source region and a drain region via a poly 5tr5 on an insulating film in a semiconductor rc having a transistor or a bipolar transistor with a base electrode extraction structure;
Or a good electrical connection to the pace area etc. is inhibited,
There is a problem in that the performance and yield of the half-βπ body IC are reduced.

Note that the above phenomenon occurs not only in field insulating films with vertical side surfaces patterned by lithography as shown in the figure, but also in field insulating films with inclined side surfaces formed by selective oxidation (LOCO3 method). Ta.

Therefore, conventionally, silicon nitride (Si
J4) A method has been attempted to eliminate the above problems by providing a film, but this has resulted in problems such as an increase in the number of manufacturing steps and an enlargement of the step difference on the substrate surface.

[Problem to be Solved by the Invention] The problem to be solved by the present invention is that in the conventional method, an epitaxial Si layer (ES) grown on the exposed surface of the silicon substrate 510 and the field insulating film 52 are grown simultaneously. The problem is that the poly-Si layer (PS) could not be grown smoothly and continuously without causing faults, and good conduction could not be achieved between the epitaxial Si layer (US) and the poly-5iN (PS).

[Means for solving problems]

The above problem can be solved by using a growth gas made by mixing a silane-based silicon source gas with a hydrogen carrier gas on a silicon substrate (1) on which an insulating film (2) is selectively formed on the surface. Vapor phase epitaxial growth of silicon is performed under reduced pressure flow of the growth gas, and the silicon substrate (1
An epitaxial silicon layer (ES) is grown on the exposed surface of the insulating film (2), and at the same time a polycrystalline silicon layer (PS) smoothly continuous with the epitaxial silicon W (ES) is grown on the insulating film (2). The problem is solved by a method of manufacturing a semiconductor device according to the present invention, which includes steps.

[For production]

That is, according to the present invention, SiO produced by a high-temperature reduction reaction of an insulating film, that is, a silicon dioxide (SiOz) film, with silane-based gas and hydrogen gas is reduced to S by reducing the pressure.
It is quickly vaporized and removed from the iO2 film surface to generate and expose a large amount of active Si growth nuclei on the SiOz film surface, and a poly-Si layer is grown on the 5in2 film via the large amount of exposed growth nuclei.

Due to the presence of a large number of growth nuclei, a smooth poly-Si layer with no faults grows on the SiO□ film, and a smooth continuous poly-Si layer without faults is formed with the epitaxial Si layer growing on the St exposed surface. Ru.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

Figures 1 (al to e) are process sectional views showing one embodiment of the method of the present invention, Figure 2 is a schematic side sectional view of a reduced pressure growth apparatus used in the method of the present invention, and Figure 3 (a). (b) is a schematic side sectional view of the vicinity of the transition region between epitaxial 5ill and poly 5iFi in the method of the present invention.

Refer to FIG. 1(a) When forming a MOS transistor with an elevated source-drain structure by the method of the present invention, for example, as shown in the same figure, selective oxidation is usually carried out on the surface of a p-type Si layer plate 1. (LOGOS) method, element formation area D
Field silicon dioxide (SiO□
) forming film 2; As usual, impurity ions are selectively implanted in advance into the field SiO□ film formation region, and the p-type channel stopper 3 is formed simultaneously with the selective oxidation.

Next, using a growth gas prepared by mixing a silane-based gas such as disilane (Sitllb) as a Si source into an H2 carrier gas, and under reduced pressure flow of the growth gas, the substrate is heated to The S discoloration is grown by vapor phase to a thickness of about 6,000 people.

Figure 2 shows an example of a land-based vacuum growth apparatus for vapor phase growth. In the figure, 31 is a base, 32 is a Pelger which is airtightly cut on the base to form a growth chamber, and 33 is a A graphite heater for heating the substrate, 34 a growth substrate, 35 a growth gas introduction tube, 36 a flowmeter for inflowing nitrogen (N2) for substitution, 37 a flowmeter for inflowing H2 carrier gas, and 38 a Si source gas. For example, S i , It , a flow meter for inflow, 39 a vacuum exhaust port, 40 a mechanical booster pump for depressurization, 41 a rotary pump, 42 power wiring for heating the graphite heater, 43 a heating power source, 13
5 shows a shower for injecting growth gas.

The growth conditions are, for example, as follows.

Si2H6 flowff13~5 cc/m1nH2 carrier gas flow rate 10β/min Growth gas pressure
200 Torr or less Growth temperature 650-1100
℃ Refer again to FIG. 1(b) In the above-mentioned low pressure vapor phase growth of Si, an epitaxial Si layer ES is formed on the exposed element formation area DA of the Si substrate 1, and a polySi layer is formed on the field 5iOz film 2. P
However, under the above conditions, the epitaxial 5iliES on the Si substrate 1 and the poly-Si layer PS on the field 5iOz film 2 are formed smoothly and continuously without any intervening fault. (TA is the transition region between the epitaxial Si layer ES and the poly-Si layer ps) Note that if the degree of decompression of the growth gas is less than 200 Torr, which is the pressure used for normal reduced-pressure growth, there will be no problem, but it is not suitable for practical growth. In order to obtain a rate of, for example, 700 people/min or more, it is desirable that the pressure is at least 3 Torr or more.

In addition to the above, monosilane (Sills), trisilane (Sislla), etc. are also used as the silane-based St source gas.

Next, boron (B) is introduced to a desired concentration to impart p-type conductivity to the epitaxial Si layer ES and poly-Si layer PS.

FIG. 3(a) is a schematic side sectional view showing the vicinity of the transition region T^ between the epitaxial Si layer ES and the poly-Si layer ps during the above growth, and shows the epitaxial 5iJiES grown on the Si substrate 1 and the field Si island film 2. It is shown that the poly5iWJPS that grows on top grows while being connected smoothly without creating any faults.

As shown in FIG. 3(b), even when the side surfaces of the field SiO□ film 2 are vertically formed by lithography, the epitaxial Si layer BS and the poly-Si layer p
s grows smoothly connected to each other without causing any faults as in the example.

Refer to FIG. 1(C). Next, thermal oxidation is applied to the epitaxial Si layer ES and the poly5i layer PS to form a SiO□ film oxidized and deoxidized film 4 with a thickness of about 300 layers on the epitaxial Si layer ES. ) 5i (h film) A discolored VO film with a thickness of about 4,000 layers is deposited on the oxide film 4 by chemical vapor deposition (CVD).
A poly-Si layer 105 is formed, and then impurities are introduced to impart conductivity to the CVD poly 5iJi 105.

Referring to FIG. 1(d), CVD poly 5ii is then bonded by conventional glue lithographic means.
A poly-Si gate electrode 5 is formed by patterning the ios, and then, using the poly-Si gate electrode 5 as a mask, arsenic (As) is ion-implanted at a high concentration into the epitaxial Si layer ES and the poly-5iFiPS to activate the ^S. patterning by normal gluing lithography means.

Here, an n4-type source region 6, an n-type drain region 7, and a p-type channel forming region 8 are formed in the region of the epitaxial Si layer ES, and a poly-Si layer ps is formed on the field SiO2 film 2.
As a result, an n-type source pull-up region 9 having good electrical connection with the source region 6 and an n-type drain pull-up region 10 having good electrical connection with the drain region 7 are formed.

Refer to FIG. 1(e). Next, after selectively removing the exposed gate SiO□ film 4 as usual, Si for impurity blocking is deposited on the Si exposed surface.
A film 11 is formed, and then an insulating film 12 made of phosphosilicate glass (PSG) or the like is formed on the substrate by a CVD method, and a source pulling region 9 and a drain pulling region 10 are individually exposed on the insulating film 12. A contact window is formed, and a source wiring 13 and a drain wiring 14 made of At or the like are respectively formed on the contact window.

Thereafter, although not shown, an insulating cover 11i is formed, and a MOS transistor having an elevated source/drain structure is completed.

〔Effect of the invention〕

As shown in the examples above, according to the method of the present invention, when a Si layer is selectively grown by vapor phase growth on a Si substrate having an insulating film such as Sing, S s
Since the epitaxial S, 7J grown on the exposed surface and the poly-Si layer grown on the insulating film can be grown smoothly and continuously without creating a fault, the epitaxial
A very good conduction state is obtained between the layer and the poly-Si layer.

Therefore, according to the present invention, an elevated source/drain structure in which the source/drain regions are raised by a poly-Si layer on an insulating film and wiring connections are made on the poly-Si layer is provided.
Performance of semiconductor devices that reduce parasitic load and increase speed, such as IS-type semiconductor devices or bipolar transistors with a base electrode extraction structure in which an extraction electrode of the base region is formed using the above-mentioned poly-Si layer on an insulating film. and yield is improved.

[Brief explanation of the drawing]

Figure 1 (al to tel is a process sectional view showing an example of the method of the present invention, Figure 2 is a schematic side view and plan view of the reduced pressure growth apparatus used in the method of the present invention, Figure 3 (al (b) ) is a schematic side sectional view of the vicinity of the transition region between the epitaxial Si layer and the poly-Si layer in the method of the present invention, FIG. 4 is a schematic side sectional view showing the elevated source/drain structure, and FIG. 5 is the base electrode extraction structure. Fig. 6 is a schematic side sectional view showing problems with the conventional method. In the figure, 1 is a p-type Si substrate, 2 is a field SiO□ film, ES is epitaxial SiN, and ps is poly-Si. layer, TA indicates the transition area.
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Claims (1)

[Claims] On a silicon substrate (1) having an insulating film (2) selectively formed on its surface, a growth gas made by mixing a silane-based silicon source gas with a hydrogen carrier gas is used. , performing vapor phase epitaxial growth of silicon under reduced pressure flow of the growth gas, growing an epitaxial silicon layer (ES) on the exposed surface of the silicon substrate (1), and simultaneously growing the insulating film (2).
1.) A method for manufacturing a semiconductor device, comprising the step of growing a polycrystalline silicon layer (PS) smoothly continuous with the epitaxial silicon layer (ES) on the epitaxial silicon layer (ES).