JPS6393217A - Analog switch circuit - Google Patents

Abstract

PURPOSE:To improve switch-off isolation and inter-channel isolation to facilitate integrating a circuit by inserting an auxiliary switching circuit between a reference potential point and the mutual connection point between a pair of MOS transistors TRs of a main switching circuit and allowing the auxiliary switching circuit to perform the switching operation opposite to that of the main switching circuit. CONSTITUTION:Sources S1 and S2 of MOS TRs 10 and 20 of the main switching circuit are internally connected to a substrate, and input/output terminals T1 and T2 are led out from drains D1 and D2 of both MOS TRs. The auxiliary switching circuit consists of one N-channel MOS TR 30 and is inserted between a reference potential point E as the earth point and a mutual connection point J between sources S1 and S2 of both MOS TRs of the main switching circuit. The gate of the TR 30 is led out as an auxiliary gate terminal (g) and receives an auxiliary signal ss' of a switching command. TRs 10 and 20 and the TR 30 perform switching operations opposite to each other; and when the main switching circuit is opened, the mutual connection point J is connected to the reference potential point E through the TR 30, and both channels are completely isolated by the reference potential point interposed between them.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to an analog switch circuit using MOS transistors for AC circuits and circuits that handle repetitive pulses, and particularly to an analog switch circuit suitable for handling high voltage and relatively large power.

[Prior art and its problems]

The above-mentioned analog switches have recently been increasingly used for various purposes, and the frequency range of the voltage and current that can be opened and closed and the frequency of passing current is also expanding. As is well known, the advantage is that even if the switching capacitance is relatively large, a small MOS transistor can be used, making it easy to integrate into an integrated circuit.
Another advantage is that high-frequency power can be switched on and off at a high switching frequency. Recent high-performance analog switches have, for example, 100 to 200 V, IA repetition angular wave number 10.
It is possible to intermittent high power pulses on the order of MHz at a switching frequency of several tens of kHz. However, when trying to integrate a large number of such high-performance analog switches (for example, 10 or more) onto a semiconductor substrate that is only a few square inches, various problems arise.One of the problems is called switch-off isolation. This is a problem of separation between input and output terminals when an open circuit occurs, and the higher the voltage handled and the higher the frequency of the passing current, the more likely it is that signals will leak from an analog switch that is supposed to be open. Another problem is the problem of isolation between channels, and as the passing current frequency and switching frequency become higher, operational interference occurs between multiple analog switches integrated on the same board. , opening/closing errors are more likely to occur. The root cause of this problem is that the input and output terminals of a single analog switch are connected via the board even when it is off, and multiple analog switch channels are also always connected via the board. It comes down to. Conventionally known solutions to this type of problem include, for example, interposing a separation layer between channels or surrounding each channel section with a guard ring, but these methods are expensive. From an integration standpoint, f! This is not necessarily an advantageous solution since it requires a significant substrate area, and it cannot be an improvement in the aforementioned switch-off isolation.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog switch circuit that has good switch-off isolation and inter-channel isolation and is easy to integrate.

[Key points of the invention]

In the present invention, there is provided a main switching circuit consisting of a pair of MOS transistors in which analog switch circuits are connected in series with each other and whose gates commonly receive switching commands, and a connection point between the two MO3 transistors and a reference potential point. The above object is achieved by constructing an auxiliary switching circuit which is inserted between the main switching circuits and always performs opening/closing operations opposite to those of the main switching circuits. The reference potential point referred to in the above-mentioned configuration may normally be the ground potential point, while the
Since the interconnection point of a pair of MOS transistors is usually at the same potential as the substrate or the well layer in the substrate, with the above configuration, when the analog switch is off, the auxiliary switching circuit is turned on and the substrate or well layer is at the reference potential. The channel, which is the current path in the two MO3 transistors, is located at the input terminal or output terminal side of the well layer at or near the interconnection point placed at this reference potential, respectively,
In addition, as is well known, since it is formed on the surface of the substrate, when the analog switch is off, both channels are connected to the reference potential point interposed between them or the base within the substrate. 1 is completely isolated by the potential @IIk71. Therefore, even if an overvoltage is applied to the input/output terminals for some reason and, in the worst case scenario, a temporary so-called punch-through occurs on the input or output side channel, all the punch-through current will be bypassed to the reference potential point, and the input/output terminals will be bypassed. This is the main reason why the switch-off isolation of the analog switch circuit according to the invention is good. On the other hand, with regard to inter-channel isolation, the most dangerous situation to be avoided is when one analog switch is in the OFF state and is interfered with by the on/off operation of a nearby analog switch, causing it to mistakenly turn on. However, in the present invention, even if a temporary ON state occurs due to interference, punch-through between the input and output terminals does not occur as described above, so the most dangerous situation described above is at least avoided, and the interference Since the energy of signals and noise is originally weak, it is immediately consumed when channel punch-through occurs, and channel punch-through is recovered after a short time. Conversely, when an analog switch is in the on state, the channels of both MO3 transistors are in a low impedance state, so there is very little risk of interference from the outside. Simultaneously with the ON operation of the main switching circuit of the switch, the auxiliary switching circuit enters the OFF state, and the aforementioned interconnection point and the semiconductor region in its vicinity are released from the reference potential. Please refer to the next section for a preferred embodiment of the circuit of the present invention.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure shows the basic circuit of the present invention in which an N-channel type is used for the MOS transistors 10 and 20 of the main switching circuit.
The sources SL, S2 of both MOS transistors 10.20 are internally connected to the substrate as shown in the figure, as is customary, and the drains 01.02 of both MOS transistors are connected to input/output terminals T1. Ding2 has been derived. Since this main switching circuit is symmetrical as shown, the input/output terminals Tl and T2
G1 and G2 are connected in common and are led out as the gate terminal G. of course,
Both MOS transistors are usually enhancement type,
Positive polarity opening/closing command SS given to gate terminal G
It closes or opens depending on the high or low state of AC voltage. Can pass electric current. In principle, the auxiliary switching circuit may be provided outside the substrate on which the main switching circuit is integrated, but it is of course advantageous to integrate it on the same substrate, and in the example of FIG.
Consisting of S transistor 30, both MO3 of the main switching circuit
It is inserted between the interconnection point J of the sources 31, 32 of the transistors and the reference potential point E, which is the ground point in the figure. The source S of this MOS transistor 30 is also internally connected to the substrate and connected to the reference potential point, and the drain d on the side opposite to the substrate is connected to the interconnection point J in the above-mentioned main switching circuit. The gate of the MO3 transistor is led out as an auxiliary gate terminal g, and receives the aforementioned auxiliary signal SS of the opening/closing command. As can be easily seen, both the MOS transistors 10 and 20 of the main switching circuit and the MOS transistor 30 of the auxiliary switching circuit perform opposite opening and closing operations, and when the main switching circuit is open, the interconnection point J is a MOS transistor.
It is connected to the reference potential point E via the transistor 3G, and conversely, when the main switching circuit is closed, the point J is connected to the reference potential point E by the MOS transistor 30 in a high impedance state. When the main switching circuit is closed, it is highly unlikely that the potential of the interconnection J will completely float from the outside, but the interconnection point should have a high impedance that does not interfere with the ON operation of both MO3 transistors 10 and 20. It is safer to connect J to the reference potential point E just in case. Figure 2 shows both M and M corresponding to Figure 1 of the main switching circuit at the bottom.
This is a cross-sectional view showing a state in which O3I-transistors 10.20 are integrated in the substrate 1, and above the cross-sectional view, an example of an auxiliary switching circuit suitable for integration in the same substrate is shown in circuit form. . As is well known, this type of M
The OS transistor 10°20 has a gate oxide II attached to the surface of the substrate 1! A gate electrode 3 made of polysilicon or aluminum is arranged on the source JiS1. S2
and drain layer DI. 02 is fabricated as an N"-doped region in the substrate 1, which is also a P-type well. The surface of most of the substrate 1 and the top surface of the gate electrode 3 is covered with another oxide film 4, which is deposited through the window. Terminals are taken from the aluminum electrode pJ15.・6.The aluminum electrode 5 is for the input/output terminals Tl and T2 in contact with the drain layer 01.02, and the aluminum electrode 6 is connected to the source jis1.S2 and the substrate 1. This is for series connection of both MO3 transistors that are in contact with each other, and this becomes the interconnection point J. When turned on, an open/close command given to the gate electrode 3 causes an N-type channel ch to be induced between the drain and source on the surface of the substrate l, causing a passing current. Allowed, but input/output terminal T when off
The voltage applied between drain 11111. It is shared by the junction between one of D2 and the substrate 1, which is a well. That is, when the terminal T1 has a more positive potential than the terminal T2, the voltage is shared by the junction on the drain NDl side, and conversely, when the terminal T2 has a more positive potential than the terminal T1, the voltage is shared by the drain NDl side junction. This is shared by the bonding on the layer 02 side. Therefore, as shown in the figure, the junctions on the drain JIDI and D2 sides are constructed so that their dimensions and curvature can withstand higher pressure than the junctions on the source layer side, and the well layer, which is the P-type substrate 1, also has a high resistivity. The design is such that when a positive potential is applied to the drain and the junction with the well becomes reverse biased, the depletion layer as shown in the figure tends to extend toward the well. Now, when the main switching circuit is open, a reference potential is applied to the interconnection point J via the closed MOS transistor 30 of the auxiliary switching circuit shown at the top of the figure, but this base t1!
Some care must be taken in selecting the potential point. That is, as shown in Figure 1, the terminal T2 is on the power supply side, and the voltage V
Assuming that an alternating current voltage as shown by In this case, the power supply is short-circuited through the high-resistance substrate 1. To avoid this, either apply a positive bias to the power supply so that the voltage V is always more positive than the reference potential point E, or On the other hand, it is sufficient to use a point with a negative bias as the reference potential point.If necessary, a coupling capacitor can be installed on the output terminal side to reduce the load. It is possible to block it from being applied. Of course, the positive/negative relationship of this potential is opposite to the above when the MOS transistor of the main switching circuit is a P-channel type. Furthermore, if the terminal T1 in Fig. 1 is on the power supply side and receives a repeated pulse voltage of constant polarity as shown in the figure, there is no problem; the reference potential point in this case is the return path of the t current to the power supply. point, typically the ground potential point of the power supply. Another MOS transistor 4] shown in FIG. 2 receives an opening/closing command ss to the gate terminal G of the main switching circuit at its gate, and outputs a supplementary signal SS of the opening/closing command from the connection point with the resistor 42 as a reference potential point. This is an inverter applied to the gate of the MO3 transistor 30 for connection. This MOS transistor 41
The resistor 42 can also be integrated in the substrate 1 for the main switching circuit together with the MOS transistor 3o, and in this case, it is preferable that the resistor 42 is also integrated at the same time as a known resistor-connected MOS transistor. When integrated on the substrate, the MO3I transistors 30 and 41 may all be small, and the number of MO3I transistors 30, 41 including the resistor 42 is about three, so it is not necessary to allocate a very large area on the substrate. Note that when an inductive load is rapidly cut off by an analog switch circuit, an oscillating voltage is generated on the load side, but in the circuit of the present invention, when the load side voltage becomes negative, the drain layer junction of the load side MO3 transistor of the main switching circuit is Since it becomes a forward bias and effectively absorbs the negative voltage to the reference potential point side and reduces the oscillating voltage, the analog switch is less likely to be damaged by the back electromotive force on the load side. [Effects of the Invention] As explained above, in the present invention, for example, another MOS transistor is connected as an auxiliary switching circuit between the interconnection point of a pair of MOS transistors in the main switching circuit of an analog switch and the reference potential point. By inserting a transistor, the opening/closing operation is opposite to the opening/closing of the main switching circuit by the opening/closing command, so that when the main switching circuit is opened, the interconnection point of the MOS transistors is connected to the 75'$ potential point, Even if you make a mistake, the voltage or current from the power supply terminal will not leak to the load terminal side, and the switch-off isolation characteristics of the analog switch will be significantly improved compared to the conventional one. Since the voltage is also improved, even high-power and high-frequency analog switches can be configured into two 5fI circuits with high density.Also, when the main switching circuit is turned on, the interconnection point is disconnected from the reference potential point. Therefore, even in the prototype results, the on-state characteristics, especially the closing speed, are not worse than those of conventional analog switches.In this way, the circuit of the present invention is especially suitable for high voltage and large current applications and operates at a high switching frequency. It is suitable for analog switches and is expected to contribute to further expanding its range of application.

[Brief explanation of the drawing]

All figures are for explanation of the present invention. Figure 1 is a principle circuit diagram showing a typical embodiment of an analog switch circuit according to the present invention, and Figure 2 shows a different embodiment thereof, together with a cross section of a MOS transistor in the main switching circuit. In Figure 0, which is a schematic circuit diagram, 1: semiconductor substrate, 10.20: 1 constituting the main switching circuit.
Pair of MOS transistors, 30: MOS transistor forming an auxiliary switching circuit, 41: MOS transistor forming a part of the auxiliary switching circuit, 42: Resistor or resistance-connected tlEM OS transistor, ch: channel, DI
, 02. d Nidrein, E: Reference potential point, Gl. G2: Gate, G: Gate terminal for main switching circuit, g
: Auxiliary gate terminal for the auxiliary opening/closing circuit, ss: Opening/closing command, SS: Supplementary signal of the opening/closing command, Sl, S2. s: source, Tl, T2: analog switch input/output terminal. Figure 1 Figure 2

Claims (1)

[Claims] 1) A main switching circuit consisting of a pair of MOS transistors connected in series and receiving switching commands in common to their respective gates, and between the interconnection point of both MOS transistors and a reference potential point. An analog switch circuit comprising an auxiliary switching circuit that is inserted into the main switching circuit and always performs switching operations opposite to those of the main switching circuit. 2) An analog switch circuit according to claim 1, wherein the auxiliary switching circuit is a MOS transistor whose gate receives a complementary signal of the switching command. 3) An analog switch circuit according to claim 1, wherein the reference potential point is selected such that the power supply voltage is always applied to the power supply side terminal of the main switching circuit with a predetermined polarity. 4) An analog switch circuit according to claim 1, characterized in that it is used for a repetitive pulse circuit that always has a predetermined polarity.