JPS63253718A - Gate circuit - Google Patents

Abstract

PURPOSE:To surely prevent malfunction by compensating an output point level of a transistor (TR) constituting a gate by the charge/discharge of the output point due to the conduction of a 2nd TR. CONSTITUTION:A 1st TR 1 constitutes a switching gate and an input signal In passes synchronously with the clock pulse phi as the switching input. The 2nd TR 10 is conducted synchronously with the clock pulse phi as the switching input and before the 1st TR 2 is conductive, the output point P is charged to compensate the high level of the input signal In. Thus, an output having an optimum level is extracted and if the logic circuit such as an inverter 6 exists in the next-stage, the malfunction due to the fluctuation of the input threshold voltage is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate circuit using a single transistor as a switching gate.

[Conventional technology]

Conventionally, as shown in FIGS. 6A and 6B, a gate circuit using a single n-channel transistor 2 or a single p-channel transistor 4 has been used.

In the gate circuit shown in FIG. 6(A), the clock pulse φ is used to make four transistors 2 conduct, and when they are turned on, the input signal In is passed through, and the passed input signal In is inverted by the inverter 6 and output. It can be taken out as an Op.

In addition, in the gate circuit shown in FIG. 6(B), the inverted clock pulse 7 is used to make the transistor 4 conductive, and when the transistor 4 is conductive, the input signal In is passed through, and the input signal In
can be inverted by the inverter 6 and taken out as the output Op.

[Problem that the invention seeks to solve]

By the way, when the gate circuit shown in FIG. 6(A) is used, the high (H)
If the level section is reduced by the amount of the threshold voltage vTH of transistor 2 plus the body bias effect at point P on the output side of transistor 2, and if the gate circuit shown in FIG. 6(B) is used, transistor 4 The low (L) level section of the input signal In that has passed through the transistor 4
At point P on the output side of the transistor 4, the voltage decreases only to the threshold voltage vTM of the transistor 4 plus the body bias effect, and a malfunction may occur due to fluctuations in the input threshold voltage of the inverter 6 at the next stage.

Therefore, the present invention attempts to prevent malfunction by compensating the gate output level of a gate circuit using such a single l transistor.

[Means for solving problems]

As shown in FIG. 1, the gate circuit of the present invention includes a first transistor (transistor 2) that passes an input signal In in accordance with a switching input (clock pulse φ), and a signal level that passes through the first transistor. and a second transistor (transistor 10) that compensates for the switching input according to the switching input.

[For production]

The first transistor (transistor 2) constitutes a switch noting gate, and passes the input signal In in synchronization with the switching input.

The second transistor (transistor 10) is
It becomes conductive in synchronization with the switching input, charges the output point P before the first transistor 2 becomes conductive, and compensates for the H level of the input signal In.

As a result, an output with an optimal level is taken out, and if a logic circuit such as the inverter 6 is present in the next stage, malfunctions due to fluctuations in the input threshold voltage are prevented.

〔Example〕

FIG. 1 shows an embodiment of the gate circuit of the present invention.

The gate circuit 8 includes a first transistor 2 as a switching gate that passes an input signal In in response to a clock pulse φ as a switching input, and a second transistor 10 that compensates the level of its output point P. . That is, the first transistor 2 has n
It is composed of channel type transistors, and is shown as A in Figure 2.
In synchronization with a clock pulse φ as a switching input applied to the gate shown in FIG. 2, conduction and interruption are performed as shown in FIG. 2B. Further, the second transistor 10 is composed of a p-channel transistor, and operates as shown in C in FIG. 2 in synchronization with a clock pulse φ as a switching input applied to the gate shown in A in FIG. Repeats conduction and cutoff alternately.

Therefore, when the input signal in shown at D in FIG. 2 is applied, the input signal In passes through the transistor 2 when the transistor 2 is turned on by the clock pulse φ. At this time, the voltage level at the output point P is charged to the H level due to the conduction of the transistor 10 just before it, and if the input signal In to the transistor 2 is at the H level, the transistor 2 is not conductive, and as a result, This is equivalent to the H level of the input signal In being electrically connected to the output point P. That is, the second
In the figure, times T+, Ts, T? Then, due to the conduction of transistor 2, the level of output point P becomes L level, and at time Tz, Ta, Th, , Ts, output point P is charged, and at time T, transistor 2
The H level is maintained by being non-conductive. As a result,
The level of the output point P of the transistor 2, as shown at E in FIG. 2, becomes a value that sufficiently exceeds the input threshold voltage of the inverter 6, and in this embodiment, the level is the power supply voltage ■. become.

Further, when the input signal In is at the L level, the H level applied to the output point P by the conduction of the transistor IO is lowered to the L level by the conduction of the transistor 2.

In this way, the input signal In having the optimum level sufficiently compensated for by the conduction of the transistor 10 is outputted from the gate circuit 8 and applied to the inverter 6.
The malfunction of the inverter 6 can be reliably prevented, and an inverted output Op synchronized with the clock pulse φ can be obtained from the inverter 6, as shown in F in FIG.

In addition, as shown in FIG. 3, in order to pull down and compensate the level of the p-channel type first transistor 4 and its output point P, an n-channel type second transistor 1 is inserted.
2 may be placed on the ground side to form the gate circuit 8. In this way, the input signal I that has passed through the transistor 4
The level of the n L level section can be set to a value sufficiently lower than the input threshold voltage of the inverter 6, for example, the ground level.

Note that, in the conventional case, a multiplexer composed of a plurality of gate circuits is connected to each analog switch 14, as shown in FIG. ．． The inverter 6 is connected to 14□ . On the other hand, when a multiplexer is constructed using the gate circuit of the present invention, as shown in FIG. 5, a single transistor 21.2□...2n is installed at each gate, and
A second transistor 10 is installed to compensate the level of the output point P, and each transistor 21.2□...
Clock pulses fl (φ), f2(
φ)...fn(φ), and a clock pulse φ for charging may be input to the gate of the transistor 10. In this case, one of the transistors 23.2□...2n is made selectively conductive in synchronization with the clock pulse φ. According to such a multiplexer, the number of constituent elements is significantly reduced to (n+1), which is the number of gates n plus the compensation transistor 10.

〔Effect of the invention〕

According to the present invention, when the gate is configured with a single transistor, the output point level of the transistor is compensated by charging and discharging the output point due to conduction of the second transistor, so that malfunction can be reliably prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the gate circuit of the present invention,
2 is a diagram showing the operation of the gate circuit shown in FIG. 1, FIG. 3 is a circuit diagram showing another embodiment of the gate circuit of the present invention, FIG. 4 is a circuit diagram showing a conventional multiplexer, and FIG. FIG. 5 is a circuit diagram showing a multiplexer using the gate circuit of the present invention, and FIG. 6 is a circuit diagram showing a conventional gate circuit. 2.4...First transistor 1O112...Second transistor Fig. 1i Fig. 3 Fig. 4 Fig. 5

Claims (1)

[Claims] A gate circuit comprising: a first transistor that passes an input signal in accordance with a switching input; and a second transistor that compensates for the level of the signal passed through the first transistor in accordance with the switching input. .