JPH0563050B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate circuit using a single transistor as a switching gate.

[Conventional technology]

Conventionally, as shown in A and B in FIG. 6, a gate circuit using a single n-channel transistor 2 or a single p-channel transistor 4 has been used.

In the gate circuit shown in A of FIG. 6, the clock pulse φ is used to make the transistor 2 conductive, and when the transistor 2 is made conductive, the input signal In is passed through, and the passed input signal In is inverted by the inverter 6 and output.
Can be taken out as an Op.

In addition, in the gate circuit shown in FIG. 6B, the transistor 4 is made conductive using an inverted clock pulse, the input signal In is passed through when it is made conductive, and the passed input signal In is inverted by the inverter 6 to output Op. It can be extracted as

[Problem that the invention seeks to solve]

By the way, when using the gate circuit shown in A of FIG. 6, the high (H) level section of the input signal In that has passed through the transistor 2 is the threshold voltage of the transistor 2 at the point P on the output side of the transistor 2.
V _TH decreases by adding the substrate bias effect,
Furthermore, when the gate circuit shown in FIG. 6B is used, the low (L)
When the level section drops only to the threshold voltage V _TH of transistor 4 plus the body bias effect at point P on the output side of transistor 4, and malfunction occurs due to fluctuations in the input threshold voltage of inverter 6 in the next stage. There is.

Therefore, the present invention aims to prevent malfunction by compensating the gate output level of a gate circuit using such a single transistor.

[Means for solving problems]

As illustrated in FIGS. 1 to 3, the gate circuit of the present invention is connected in series to an input terminal that receives an input signal, receives the input signal, and performs switching by receiving a clock pulse at the gate. a first transistor 2 that passes the input signal in accordance with the input signal; second transistors 10 and 12 which alternately switch and shift the level of the output point of the first transistor to the power supply voltage or ground level when the first transistor is conductive according to the switching; and the input signal. , an inverter 6 that inverts and extracts the switching output appearing at the output point of the first transistor based on the switching of the first and second transistors.

[Effect]

The first transistor (transistor 2) constitutes a switching gate, and passes the input signal In in synchronization with the switching input.

Then, the second transistor (transistor 1
0) becomes conductive in synchronization with the switching input, charges the output point P before the first transistor 2 becomes conductive, and compensates for the H level of the input signal In.

As a result, an output having an optimum level is taken out, and malfunctions due to fluctuations in the input threshold voltage in the inverter 6 installed at the next stage are prevented.

〔Example〕

FIG. 1 shows an embodiment of the gate circuit of the present invention.

The gate circuit 8 includes a first transistor 2 as a switching gate that passes the input signal In in response to a clock pulse φ as a switching input, and a second transistor 2 that compensates the level of its output point P.
A transistor 10 is installed, and an inverter 6 is installed on its output side. That is, the first transistor 2 connected in series to the input terminal receiving the input signal is composed of an n-channel transistor, and is synchronized with the clock pulse φ as a switching input applied to the gate shown in A in FIG. Then conduction and cut-off are performed as shown in FIG. 2B. Further, the second transistor 10 is composed of a p-channel transistor, and in synchronization with a clock pulse φ as a switching input applied to the gate shown in A in FIG.
Repeat the conduction and cutoff alternately as shown in .

Therefore, when the input signal In shown at D in FIG. 2 is applied, the clock pulse φ causes the transistor 2 to
When the transistor 2 is conductive, the input signal In passes through the transistor 2. At this time, the voltage level at the output point P is charged to the H level due to the conduction of the transistor 10 just before it, and the input signal to the transistor 2 is
When In is at the H level, the transistor 2 is not conductive, and as a result, the result is the same as when the H level of the input signal In is conductive to the output point P. That is, the second
In the figure, at times T ₁ , T ₅ , and T ₇ , the level at output point P becomes L level due to conduction of transistor 2, and at times T ₂ , T ₄ , T ₆ , and T ₈ , the charge at output point P decreases. Further, at time _T3 , the transistor 2 is rendered non-conductive to maintain the H level. As a result, the level of the output point P of transistor 2 is
As shown at E in FIG. 2, the voltage becomes a value that sufficiently exceeds the input threshold voltage of the inverter 6, and becomes the power supply voltage V _DD in this embodiment.

Also, when the input signal In is at L level, the output point P
The H level given by conduction of transistor 10 is lowered to L level by conduction of transistor 2.

In this way, the input signal In having the optimal level that is sufficiently compensated for by the conduction of the transistor 10 is output from the gate circuit 8 and applied to the inverter 6, so that malfunctions of the inverter 6 can be reliably prevented.
As shown at F in FIG. 2, an inverted output Op synchronized with the clock pulse φ is obtained from the inverter 6.

Further, as shown in FIG. 3, in order to pull down and compensate the level of the first p-channel transistor 4 and its output point P, a second n-channel transistor 12 is placed on the ground side. In this way, the level of the L level section of the input signal In that has passed through the transistor 4 can be set to a value sufficiently lower than the input threshold voltage of the inverter 6, for example, to the ground level. can do.

Note that, in the conventional case, a multiplexer composed of a plurality of gate circuits is constructed by connecting an inverter 6 to each analog switch 14 ₁ , 14 ₂ . . . 14n, as shown in FIG _. ~14n each consists of two sets of transistors, so the number of constituent elements is 2 of the number of gates n.
It becomes 2n times. On the other hand, when a multiplexer is constructed using the gate circuit of the present invention, as shown in FIG. 5, a single transistor 2 ₁ , ₂ 2 . A second transistor 10 is installed to compensate the level of P, and each transistor 2 ₁ , 2 ₂
...2n gate clock pulse f ₁ (φ), f ₂ (φ)
...fn(φ), and a clock pulse φ for charging may be input to the gate of the transistor 10. In this case, the transistors 2 ₁ , 2 ₂ . . . 2n are
One of them is made selectively conductive in synchronization with the clock pulse φ. According to such a multiplexer, the number of constituent elements is significantly reduced to (n+1), which is the number of gates n plus the compensation transistor 10.

〔Effect of the invention〕

As explained above, according to the present invention, the first transistor that passes an input signal is repeatedly turned on and off by a clock pulse, and is installed between its output point and a high potential point or a ground potential point. Since the second transistor alternately turns on and off with the first transistor in synchronization with the clock pulse, the potential at the output point of the first transistor is transferred to the power supply voltage or ground level by the second transistor. As a result, the logic level can be made to correspond reliably to the input level on the inverter side, and the reliability of the logic operation can be improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the gate circuit of the present invention, Fig. 2 is a diagram showing the operation of the gate circuit shown in Fig. 1, and Fig. 3 is a circuit diagram showing another embodiment of the gate circuit of the invention. 4 is a circuit diagram showing a conventional multiplexer, FIG. 5 is a circuit diagram showing a multiplexer using the gate circuit of the present invention, and FIG.
The figure is a circuit diagram showing a conventional gate circuit. 2, 4...first transistor, 6...inverter, 10, 12...second transistor.

Claims (1)

[Scope of Claims] 1. A first transistor connected in series to an input terminal that receives an input signal, receives the input signal, and switches upon receiving a clock pulse at its gate, and passes the input signal in response to the switching. , is connected between the output point of the first transistor and the power supply voltage point or the ground point, receives the clock pulse at the gate and switches alternately with the first transistor, and in response to this switching, the first transistor a second transistor that shifts the level of the output point of the first transistor to the power supply voltage or ground level when the transistor is conductive; A gate circuit comprising: an inverter that inverts and takes out the switching output appearing at the output point of the transistor No. 1.