JPS6159911A - Changeover switch circuit - Google Patents

Changeover switch circuit

Info

Publication number
JPS6159911A
JPS6159911A JP18214884A JP18214884A JPS6159911A JP S6159911 A JPS6159911 A JP S6159911A JP 18214884 A JP18214884 A JP 18214884A JP 18214884 A JP18214884 A JP 18214884A JP S6159911 A JPS6159911 A JP S6159911A
Authority
JP
Japan
Prior art keywords
input terminal
field effect
effect transistor
output terminal
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18214884A
Other languages
Japanese (ja)
Inventor
Fumio Hamada
文男 濱田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18214884A priority Critical patent/JPS6159911A/en
Publication of JPS6159911A publication Critical patent/JPS6159911A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

PURPOSE:To prevent the operation of other changeover switch from being disabled even if one changeover switch of plural routes is faulty by constituting switch through the combination of an enhancement FET and a depletion FET. CONSTITUTION:When a negative voltage is fed to a control terminal 5, depletion FETs 6b, 7b are turned on, an enhancement FET8b is turned off and a signal inputted to a input terminal 3 is outputted to an output terminal 4. When a positive voltage is impressed to the terminal 5 conversely, the FETs 6b, 7b are turned off, the FET8b is turned on and no input signal is outputted to the output terminal 4. Since the FETs 6b, 7b are turned off at interruption, the impedance viewed from the terminals 3, 4 is high. Thus, in using the titled circuit as a switching circuit, since the effect on the other route is negligibly small, the switch of the active route has only to be energized by the power supply of the active route and the switch of the standby route has only to be energized by the power supply of the standby route.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、信頼性が要求される切換器、例えば多重電話
回線の切換スイ・ソチとして利用される。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is used as a switching device that requires reliability, for example, a switch for switching multiple telephone lines.

〔従来の技術〕[Conventional technology]

多重電話回線の切換に使用されるスイッチは、現用ルー
１〜と予備ルートとの結合部に使用されるので、極めて
高い信頼性が要求される。例えば、現用ルートの一部で
故障が生じた場合に、スイッチが正常であれば予備ルー
トが選択されて支障のない通信が続行されるが、スイッ
チが故障した場合には、回線断という事態が起こり得る
。The switch used for switching multiple telephone lines is used to connect the working routes 1 to 1 and the backup route, and therefore requires extremely high reliability. For example, if a failure occurs in part of the working route, if the switch is normal, the backup route will be selected and communication will continue without any problems, but if the switch fails, the line will be disconnected. It can happen.

このような用途に適合する従来例切換スイッチの構成を
第４図に示す。また、この切換スイッチが用いられた応
用例装置を第５図に示す。この従来例切換スイッチは現
用ルートか予備ルートかどちらか一方が正常であればこ
のスイッチが正常に作動するように、スイッチの電源は
現用ルートと予備ルートの両方の電源から供給されてい
た。第５図でアンテナ１−受信ａ　ＲＩ　−復調機り、
−スイッチ５Ｗ１−装置出力端子２は予備ルートで、ア
ンテナ１−受信機Ｒ２−復調機Ｄ２−スイッチＳＷ、−
装置出力端子２は現用ルートであり、通常スイッチＳ　
Ｗ　ｚが閉路状態で、スイッチＳＷ。FIG. 4 shows the configuration of a conventional changeover switch suitable for such uses. Further, FIG. 5 shows an applied example device in which this changeover switch is used. In this conventional changeover switch, power to the switch is supplied from the power sources of both the working route and the backup route so that the switch operates normally if either the working route or the backup route is normal. In Fig. 5, antenna 1 - reception a RI - demodulator,
- switch 5W1 - device output terminal 2 is a backup route, antenna 1 - receiver R2 - demodulator D2 - switch SW, -
Device output terminal 2 is the current route and is normally connected to switch S.
When Wz is closed, switch SW.

が開路状態にある。is in an open state.

ここで、復調機Ｄ２が故障し、復調機Ｄ２の電源ライン
が接地され、電源ＰＳ２が働かなくなった場合を想定す
る。この場合に、スイッチＳＷ１が閉路しスイッチＳ　
Ｗ　ｚが開路する必要がある。Here, it is assumed that the demodulator D2 fails, the power supply line of the demodulator D2 is grounded, and the power supply PS2 stops working. In this case, switch SW1 is closed and switch S
It is necessary for Wz to open.

スイッチＳＷ、およびＳＷ２は電ｍ　ｐ　ｓ　＋および
ＰＳ２から並列供給されているので、電源ＰＳｚからの
電力供給を受けなくても電源ｐ　ｓ　＋からの正常な電
力供給により回線切換が実行される。Since the switches SW and SW2 are supplied with power in parallel from the power supply m p s + and PS2, line switching is performed by normal power supply from the power supply p s + without receiving power supply from the power supply PSz.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、スイッチＳＷｚが故障しその電源ラインが接
地された場合を想定すると、スイッチＳＷ２に供給して
いる電源Ｐ　Ｓ　＋およびＰＳ、の電圧が同時に低下し
、このために受信ｉＲ，、復調機り、およびスイッチＳ
ＷＩは正常に作動しなくなり、回線断状態が出現するこ
とになる。電源の並列供給を要する従来例回路はこのよ
うな欠点がある。However, assuming that the switch SWz fails and its power line is grounded, the voltages of the power supplies P S + and PS, which are supplied to the switch SW2, decrease simultaneously, and as a result, the reception iR, demodulator , and switch S
The WI will no longer operate normally, and a line disconnection state will appear. Conventional circuits that require parallel power supply have these drawbacks.

本発明はこの欠点を除去するもので、電源の並列供給を
不要とする切換スイッチ回路を提供することを目的とす
る。The present invention aims to eliminate this drawback and provides a changeover switch circuit that does not require parallel supply of power supplies.

〔問題点をｊつ７決するための手段〕 本発明は、入力端子と、出力端子と、制御入力端子とを
（ＪＫｔえ、この制御人力θ：ｂ子の電位にしたがって
上記人カニＪ：ｉｉ子と上記出力端子との間が導通状ｆ
）またば解放状Ｈになる切換スイッチ回路で、前述の問
題点を解決するための手段として、第一のエンハンスメ
ント形電界効果トランジスタおよび第二のエンハンスメ
ント形電界効果トランジスタ各ドレイン電極およびソー
ス電極が直列に接続された上記入力端子と上記出力端子
との間に接続され、第三のディプリーション形電界効果
トランジスタのソース電極またはドレイン電極が上記第
一および第二の電界効果トランジスタのソース電極とド
レイン電極との接続点に接続され、上記第一、第二およ
び第三の電界効果トランジスタの各ゲート電極が一つの
接続点電位に共通に接続され、この接続点電位に上記制
御入力端子の信号にしたがって負電位または零電位を与
える制御回路とを備えたことを特徴とする。[Means for resolving the problems] The present invention provides input terminals, output terminals, and control input terminals (JKt, and the above-mentioned human crab J:ii There is continuity f between the output terminal and the above output terminal.
) Also, as a means for solving the above-mentioned problem in a changeover switch circuit that becomes an open state H, the drain electrode and the source electrode of each of the first enhancement type field effect transistor and the second enhancement type field effect transistor are connected in series. The source electrode or the drain electrode of the third depletion type field effect transistor is connected between the input terminal connected to the output terminal and the output terminal connected to the source electrode and the drain electrode of the first and second field effect transistors. The gate electrodes of the first, second and third field effect transistors are commonly connected to one connection point potential, and the signal of the control input terminal is connected to this connection point potential. Therefore, the present invention is characterized in that it includes a control circuit that provides a negative potential or zero potential.

また、入力端子と、出力端子と、制御入力端子とを備え
、この制御入力端子の電位にしたがって上記入力端子と
上記出力端子との間が導通状！虚または解放状態になる
切換スイッチ回路で、前述の問題点を解決するための手
段として、第一のディプリーション形電界効果トランジ
スタ、第二のディプリーション形電界効果トランジスタ
の各ドレイン電極およびソース電極が直列に接続されて
上記入力端子と上記出力端子との間に接続され、第三の
エンハンスメント形電界効果トランジスタのソース電極
またはドレイン電極が上記第一および第二の電界効果ト
ランジスタのソース電極とドレイン電極との接続点に接
続され、上記第一、第二および第三の電界効果トランジ
スタの各ゲート電極が一つの接続点電位に共通に接続さ
れ、この接続点電位に上記制御入力端子の信号にしたか
っ゛Ｃ正電位または零電位を与える制御回路どを０１ｕ
えたことを特徴とする。Also, it includes an input terminal, an output terminal, and a control input terminal, and conduction is established between the input terminal and the output terminal according to the potential of the control input terminal! As a means for solving the above-mentioned problem in a change-over switch circuit that is in an imaginary or open state, each drain electrode and source of a first depletion type field effect transistor and a second depletion type field effect transistor electrodes are connected in series between the input terminal and the output terminal, the source electrode or the drain electrode of the third enhancement mode field effect transistor being connected to the source electrode of the first and second field effect transistors; The gate electrodes of the first, second and third field effect transistors are connected to a connection point with the drain electrode, and the gate electrodes of the first, second and third field effect transistors are commonly connected to one connection point potential, and the signal of the control input terminal is connected to this connection point potential. I want to change the control circuit that gives a positive potential or zero potential to 01u.
It is characterized by the fact that

〔作用〕[Effect]

上記制御入力端子に印加される信号により、上記第一の
電界効果トランジスタおよび上記第二の電界効果１−ラ
ンジスタは導通状態になり上記第三の電界効果トランジ
スタは非導通状態になるか、または、上記第一の電界効
果トランジスタおよび上記第二の電界効果トランジスタ
は非導通状態になり上記第三の電界効果トランジスタは
４通状態になる。A signal applied to the control input terminal causes the first field effect transistor and the second field effect transistor to become conductive and the third field effect transistor to become nonconducting, or The first field effect transistor and the second field effect transistor are in a non-conducting state, and the third field effect transistor is in a quadruple state.

〔実施例〕〔Example〕

以下、本発明実施例回路を図面に基づいて説明する。 Hereinafter, a circuit according to an embodiment of the present invention will be explained based on the drawings.

第１図は、第一実施例回路の＋１、！成を示す回路接続
図である。第２図は、第二実施例回路の構成を示す回路
接続図である。第３図は、この実施例回路が用いられた
応用例装置の構成を示すブロック構成図である。FIG. 1 shows +1,! of the circuit of the first embodiment. FIG. 3 is a circuit connection diagram showing the configuration. FIG. 2 is a circuit connection diagram showing the configuration of the circuit of the second embodiment. FIG. 3 is a block diagram showing the configuration of an applied example device in which this embodiment circuit is used.

まず、第一実施例回路の構成を第１図に基づいて説明す
る。この実施例回路は、第一の電界効果トランジスタ（
以下、ＦＥＴという。）６ｂと、第二（７）ＦＥＴ７ｂ
と、第三（７）ＦＥＴａｂと、制御回路９と、入力端子
３と、出力端子４と、制御■端子５とを備え、ここで、
第一のＦＥＴ６ｂおよび第二のＦＥＴ７ｂはエンハンス
メント形ＭＯ５ｌｉＥＴであり、第三のＦＥＴａｂはデ
ィプリーション形ＭＯ５ＦＥＴである。First, the configuration of the circuit of the first embodiment will be explained based on FIG. This example circuit consists of a first field effect transistor (
Hereinafter referred to as FET. )6b and the second (7) FET7b
, a third (7) FETab, a control circuit 9, an input terminal 3, an output terminal 4, and a control terminal 5, where:
The first FET6b and the second FET7b are enhancement type MO5liETs, and the third FETab is a depletion type MO5FET.

入力端子３は第一のＩ”ＥＴ６ｂのソースに接続され、
第一のＦＥＴ６ｂのドインは第二のＦＥＴ７ｂのドレン
および第三のＦＥＴ８ｂのドレンに接続される。Input terminal 3 is connected to the source of the first I"ET6b,
The input of the first FET 6b is connected to the drain of the second FET 7b and the drain of the third FET 8b.

制御端子５は制御回路９の入力に接続され、制御回路９
の出力は第一のＦＥＴ６ｂのゲート、第二のＦＥＴ７ｂ
のゲートおよび第三のＦＥＴａｂのゲートに接続される
。第三のＦＥＴ８ｂのソースば共通電位に接続され、第
二のＦＥＴ７ｂのソースは出力端子４に接続される。The control terminal 5 is connected to the input of the control circuit 9.
The output of is the gate of the first FET6b, the second FET7b
and the gate of the third FETab. The source of the third FET 8b is connected to the common potential, and the source of the second FET 7b is connected to the output terminal 4.

次に、この実施例回路の動作を第１図に基づいて説明す
る。Next, the operation of this embodiment circuit will be explained based on FIG.

、、＋＋ｉ子５にマイナス電圧を印加した場合には、Ｆ
ＥＴ６ｂおよびＦＥＴ７ｂがオン状態になり、かつＦＥ
Ｔａｂはオフ状態になる。したがって、端子３および端
子４間は導通状態になる。端子５に地気信号を入力した
場合にはＦＥＴ６ｂおよびＦＥＴ７ｂがオフ状態になり
、ＦＥＴａｂがオン状態になり、端子３および端子４間
は回路状態になる。電源断状態では、ＦＥＴ６ｂ、７ｂ
および８ｂのゲートに地気信号が与えられるか、または
オープン状態になったことと当価であるので、ＦＥＴ６
ｂおよび７ｂはオフ状態になり、ＦＥＴ８ｂはオン状態
になり、したがって端子３および端子４間は断路状態に
なる。このように、ＦＥＴ６ｂおよびＦＥＴ７ｂがオフ
状Ｂになるので、端子３および４から見たインピーダン
スが高インピーダンスになり、第３図の応用例装置のス
イッチＳ　Ｗ　＋およびＳＷ２にこの実施例回路を用い
た場合に、他ルートに与える影Ｖは無視できる程度に小
さい。したがって、電源オフ時でも他ルートに影響を与
えないので、この実施例回路は片電源で使用できる。す
なわぢ、電源の供給関係は、第２図に示すように、現用
ルートのスイッチは現用ルートの電源で、予備ルートの
スイッチは予備ルートの電源で電力供給されればよいこ
とになる。,,++ When a negative voltage is applied to the i-element 5, F
ET6b and FET7b are turned on and FE
Tab is turned off. Therefore, the terminal 3 and the terminal 4 are electrically connected. When an earth signal is input to terminal 5, FET6b and FET7b are turned off, FETab is turned on, and a circuit is established between terminals 3 and 4. In the power-off state, FET6b, 7b
Since it is equivalent to the ground signal being given to the gate of and 8b or being in the open state, FET6
b and 7b are turned off, FET 8b is turned on, and terminals 3 and 4 are therefore disconnected. In this way, since FET6b and FET7b are in the OFF state B, the impedance seen from terminals 3 and 4 becomes high impedance, and this example circuit can be used for switches SW + and SW2 of the application example device in FIG. In this case, the influence V on other routes is so small that it can be ignored. Therefore, since other routes are not affected even when the power is turned off, this embodiment circuit can be used with a single power supply. In other words, regarding the power supply relationship, as shown in FIG. 2, the switches on the working route should be powered by the power supply on the working route, and the switches on the backup route should be powered by the power supply on the backup route.

次に、第二実施例回路を第２図に基づいて説明する。こ
の実施例回路は第一実施例回路のエンハンスメント形Ｆ
ＥＴ６ｂおよび７ｂをディプリーション形ＦＥＴ６ｃお
よび７ｃとし、ディプリーション形ＦＥＴ８ｂをエンハ
ンスメント形Ｆ　Ｅ　Ｔ　８ｃとしたものであり、また
、第一実施例回路では、制御端子５の信号にしたがって
、それぞれのＦＥＴ６ｂ、７ｂおよび８ｂのゲートに負
電位または零電位が与えられるが、この第二実施例回路
では正電位または零電位が与えられて第一実施例回路と
同様の動作が行われる。Next, a second embodiment circuit will be explained based on FIG. 2. This embodiment circuit is an enhancement type F of the first embodiment circuit.
ET6b and 7b are depletion type FETs 6c and 7c, and depletion type FET8b is an enhancement type FET8c. A negative potential or zero potential is applied to the gates of FETs 6b, 7b and 8b, but in this second embodiment circuit, a positive potential or zero potential is applied and the same operation as in the first embodiment circuit is performed.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、エンハンスメント形Ｆ
ＥＴとディプリーション形ＦＥＴとを組合せたスイッチ
を構成することにより、一方の切換スイッチの故障によ
り、他方の切換スイッチの作動が不能にならない盲信！
ＩＩ性を有する切換スイッチ回路を実現する効果がある
。As explained above, the present invention provides enhancement type F
By configuring a switch that combines an ET and a depletion type FET, you can be confident that a failure in one changeover switch will not make the other changeover switch inoperable!
This has the effect of realizing a changeover switch circuit having II characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は第一実施例回路の構成を示す回路接続図。 第２図は第二実施例回路の構成を示す回路接続図。 第３図は実施例回路が用いられた応用例装置の構成を示
すブロック構成図。 第４図は従来例回路の構成を示す回路接続図。 第５図は従来例回路が用いられた応用例装置の構成を示
すブロック構成図。 ■・・・アンテナ、２・・・装置出力端子、３・・・入
力端子、４・・・出力端子、５・・・制御端子、６ａ、
７ａ、８ａ、６ｂ、７ｂ、８ｂ・・・ＦＥＴ、９・・・
制御回路、１０．１１・・・インバータ、Ｄ、　、Ｄｚ
・・・復８周機、Ｐ　Ｓ＋　、Ｐ　Ｓｚ・・・電源、Ｒ
＋、Ｒｚ・・・受信機、ＳＷ　＋　、Ｓ　Ｗ　ｚ、ＳＷ
３　、ＳＷ４　・・・スイッチ。FIG. 1 is a circuit connection diagram showing the configuration of the circuit of the first embodiment. FIG. 2 is a circuit connection diagram showing the configuration of the circuit of the second embodiment. FIG. 3 is a block diagram showing the configuration of an applied example device in which the example circuit is used. FIG. 4 is a circuit connection diagram showing the configuration of a conventional circuit. FIG. 5 is a block diagram showing the configuration of an applied example device using the conventional circuit. ■... Antenna, 2... Device output terminal, 3... Input terminal, 4... Output terminal, 5... Control terminal, 6a,
7a, 8a, 6b, 7b, 8b...FET, 9...
Control circuit, 10.11... Inverter, D, , Dz
...8-round machine, P S+, P Sz ... power supply, R
+, Rz...receiver, SW +, SW z, SW
3, SW4...Switch.

Claims (2)

【特許請求の範囲】[Claims] （１）入力端子と、出力端子と、制御入力端子とを備え
、 この制御入力端子の電位にしたがって上記入力端子と上
記出力端子との間が導通状態または解放状態になる切換
スイッチ回路において、 第一のエンハンスメント形電界効果トランジスタおよび
第二のエンハンスメント形電界効果トランジスタの各ド
レイン電極およびソース電極が直列に接続された上記入
力端子と上記出力端子との間に接続され、 第三のデイプリーション形電界効果トランジスタのソー
ス電極またはドレイン電極が上記第一および第二の電界
効果トランジスタのソース電極とドレイン電極との接続
点に接続され、 上記第一、第二および第三の電界効果トランジスタの各
ゲート電極が一つの接続点電位に共通に接続され、 この接続点電位に上記制御入力端子の信号にしたがって
負電位または零電位を与える制御回路を備えたことを特
徴とする切換スイッチ回路。(1) A changeover switch circuit comprising an input terminal, an output terminal, and a control input terminal, and in which the input terminal and the output terminal are in a conductive state or a disconnected state according to the potential of the control input terminal, each drain electrode and source electrode of a first enhancement type field effect transistor and a second enhancement type field effect transistor are connected between the input terminal and the output terminal connected in series, and a third depletion type field effect transistor is connected between the input terminal and the output terminal connected in series; A source electrode or a drain electrode of the field effect transistor is connected to a connection point between the source electrode and the drain electrode of the first and second field effect transistors, each gate of the first, second and third field effect transistor. A changeover switch circuit characterized in that the electrodes are commonly connected to one connection point potential, and the control circuit provides a negative potential or zero potential to the connection point potential in accordance with a signal from the control input terminal. （２）入力端子と、出力端子と、制御入力端子とを備え
、 この制御入力端子の電位にしたがって上記入力端子と上
記出力端子との間が導通状態または解放状態になる切換
スイッチ回路において、 第一のデイプリーション形電界効果トランジスタおよび
第二のデイプリーション形電界効果トランジスタの各ド
レイン電極およびソース電極が直列に接続されて上記入
力端子と上記出力端子との間に接続され、 第三のエンハンスメント形電界効果トランジスタのソー
ス電極またはドレイン電極が上記第一および第二の電界
効果トランジスタのソース電極とドレイン電極との接続
点に接続され、 上記第一、第二および第三の電界効果トランジスタの各
ゲート電極が一つの接続点電位に共通に接続され、 この接続点電位に上記制御入力端子の信号にしたがって
正電位または零電位を与える制御回路を備えたことを特
徴とする切換スイッチ回路。(2) A changeover switch circuit comprising an input terminal, an output terminal, and a control input terminal, and in which the input terminal and the output terminal are in a conductive state or an open state according to the potential of the control input terminal, Each drain electrode and source electrode of the first depletion type field effect transistor and the second depletion type field effect transistor are connected in series between the input terminal and the output terminal, and the third depletion type field effect transistor is connected in series between the input terminal and the output terminal. A source electrode or a drain electrode of the enhancement type field effect transistor is connected to a connection point between the source electrode and the drain electrode of the first and second field effect transistors, and A change-over switch circuit characterized in that each gate electrode is commonly connected to one connection point potential, and includes a control circuit that applies a positive potential or zero potential to the connection point potential in accordance with a signal from the control input terminal.
JP18214884A 1984-08-30 1984-08-30 Changeover switch circuit Pending JPS6159911A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18214884A JPS6159911A (en) 1984-08-30 1984-08-30 Changeover switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18214884A JPS6159911A (en) 1984-08-30 1984-08-30 Changeover switch circuit

Publications (1)

Publication Number Publication Date
JPS6159911A true JPS6159911A (en) 1986-03-27

Family

ID=16113196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18214884A Pending JPS6159911A (en) 1984-08-30 1984-08-30 Changeover switch circuit

Country Status (1)

Country Link
JP (1) JPS6159911A (en)

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