JPH0529997B2 - - Google Patents
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- Publication number
- JPH0529997B2 JPH0529997B2 JP26670285A JP26670285A JPH0529997B2 JP H0529997 B2 JPH0529997 B2 JP H0529997B2 JP 26670285 A JP26670285 A JP 26670285A JP 26670285 A JP26670285 A JP 26670285A JP H0529997 B2 JPH0529997 B2 JP H0529997B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- power supply
- contact
- fet
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000009792 diffusion process Methods 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 5
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 101150015217 FET4 gene Proteins 0.000 description 4
- 101100119059 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) ERG25 gene Proteins 0.000 description 3
- 101150073536 FET3 gene Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 101150079361 fet5 gene Proteins 0.000 description 2
Landscapes
- Read Only Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、CMOSEPROMの電源切換回路に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power supply switching circuit for CMOS EPROM.
〔従来の技術〕
第４図は従来用いられているこの種の電源切換
回路の回路図で、１，２，３，４はＰチヤネル
FET、５，６はｎチヤネルFETである。FET１
のソースは電源（Vpp）につながり、ゲートは
FET３のドレインとFET５のドレインとの接点
Ａにつながり、ドレインは出力端子（Vpp／Vcc）
につながつている。FET２のソースは電源
（Vcc）につながり、ゲートはFET４のドレイン
とFET６のドレインとの接点Ｂにつながり、ド
レインは出力端子（Vpp／Vcc）につながつてい
る。FET３のソースは電源（Vpp）につながり、
ゲートは接点Ｂにつながり、ドレインは接点Ａに
つながつている。[Prior art] Figure 4 is a circuit diagram of this type of power switching circuit that has been used conventionally, and 1, 2, 3, and 4 are P channels.
FETs 5 and 6 are n-channel FETs. FET1
The source of is connected to the power supply (V pp ), and the gate is
Connected to contact A between the drain of FET3 and the drain of FET5, and the drain is the output terminal (V pp /V cc )
connected to. The source of FET2 is connected to the power supply ( Vcc ), the gate is connected to contact B between the drain of FET4 and the drain of FET6, and the drain is connected to the output terminal ( Vpp / Vcc ). The source of FET3 is connected to the power supply (V pp ),
The gate is connected to contact B, and the drain is connected to contact A.
FET４のソースは電源（Vpp）につながり、ゲ
ートは接点Ａにつながり、ドレインは接点Ｂにつ
ながつている。FET５のドレインは接点Ａにつ
ながり、ゲートには切換信号（PGM）が入力さ
れ、ソースは電源（Vss）につながつている。
FET６のドレインは接点Ｂにつながり、ゲート
には切換信号（PGM）を反転したものが入力さ
れ、ソースは電源（Vss）につながつている。
FET１，２，３，４の基条は電源（Vpp）につな
がつている。FET５，６の基板は電源（Vss）に
つながつている。第５図にFET１およびFET２
の断面図を示す。 The source of FET4 is connected to the power supply ( Vpp ), the gate is connected to contact A, and the drain is connected to contact B. The drain of FET5 is connected to contact A, the switching signal (PGM) is input to the gate, and the source is connected to the power supply ( Vss ).
The drain of FET6 is connected to contact B, the inverted switching signal (PGM) is input to the gate, and the source is connected to the power supply (V ss ).
The bases of FETs 1, 2, 3, and 4 are connected to the power supply ( Vpp ). The substrates of FETs 5 and 6 are connected to a power supply (V ss ). Figure 5 shows FET1 and FET2.
A cross-sectional view is shown.
次に動作について説明する。Vpp＜Vccの場合
は第５図からわかるように、電源（Vcc）から
FET２のソースおよび基板を通して電源（Vpp）
へ短絡してしまうので、Vpp＜Vccでは使用でき
ない。Vpp≧Vccの場合は、FET２のソースと基
板とは逆バイアスになるので短絡しない。この場
合に、切換信号（PGM）が“Ｈ”であればFET
５は導通し、接点Ａは“Ｌ”となり、FET１は
導通する。一方、FET６のゲートには切換信号
（PGM）を反転した“Ｌ”が入つているので非導
通となり、FET４のゲートは接点Ａとつながり
“Ｌ”となつているのでFET４は導通し、接点Ｂ
は“Ｈ”となつてFET２は非導通となる。した
がつて、出力端子（Vpp／Vcc）には電源電圧Vpp
が出力される。これに対し、切換信号（PGM）
が“Ｌ”になると上記のまつたく逆となり、接点
Ａは“Ｈ”、接点Ｂは“Ｌ”となるのでFET１は
非導通、FET２は導通し、出力端子（Vpp／Vcc）
には電源電圧Vccが出力される。 Next, the operation will be explained. If V pp <V cc , as shown in Figure 5, the power supply (V cc )
Power supply (V pp ) through the source of FET2 and the board.
It cannot be used when V pp < V cc because it will short-circuit to. If V pp ≧ V cc , the source of FET2 and the substrate will be reverse biased, so there will be no short circuit. In this case, if the switching signal (PGM) is “H”, the FET
5 is conductive, contact A becomes "L", and FET1 is conductive. On the other hand, since the gate of FET6 receives "L" which is the inversion of the switching signal (PGM), it becomes non-conductive, and the gate of FET4 connects to contact A and becomes "L", so FET4 conducts and contact B
becomes "H" and FET2 becomes non-conductive. Therefore, the power supply voltage V pp is applied to the output terminal (V pp /V cc ).
is output. In contrast, the switching signal (PGM)
When becomes "L", the above is completely reversed, contact A becomes "H" and contact B becomes "L", so FET1 is non-conducting, FET2 is conducting, and the output terminal (V pp /V cc )
The power supply voltage Vcc is output.
従来の電源切換回路は以上のように構成されて
いるので、Vpp＜Vccでは使用できない欠点があ
つた。
Since the conventional power supply switching circuit is configured as described above, it has a drawback that it cannot be used when V pp <V cc .
この発明は上記のような問題点を解消するため
になされたもので、VppとVccの大小関係に関係
なく使用できるCMOSEPROMの電源切換回路を
提供することにある。 The present invention has been made to solve the above-mentioned problems, and its object is to provide a CMOSEPROM power supply switching circuit that can be used regardless of the magnitude relationship between V pp and V cc .
この発明に係る電源切換回路は、第１導電型の
半導体基板２１上に設けられた第２導電型の第１
の拡散層２２と第２の拡散層２２と、その第１の
拡散層上に設けられ、第１の電源（Vpp）が供給
される第１導電型の第３の拡散層２３と、第２の
拡散層上に設けられ、第２の電源（Vcc）が供給
される第１導電型の第４の拡散層２３と、第１の
拡散層２２と第２の拡散層２２にそれぞれ設けら
れ、互いに切り換え出力端子に接続されている第
１導電型の第５の拡散層２４と第６の拡散層２４
と、第３の拡散層２３と第５の拡散層２４の間に
絶縁層２５を介して設けられ、第１の制御信号Ａ
が印加する第１の制御電極２６と、第４の拡散層
２４と第６の拡散層２３の間に絶縁層２５を介し
て設けられ、第２の制御信号Ｂが印加する第２の
制御電極２６とを有し、第１の制御信号Ａと第２
の制御信号Ｂを出力する制御信号発生手段が、第
１の電源（Vpp）か第２の電源（Vcc）の電圧の
高い電源により動作するようにしたものである。
The power supply switching circuit according to the present invention includes a first semiconductor substrate 21 of a second conductivity type provided on a semiconductor substrate 21 of a first conductivity type.
a third diffusion layer 23 of the first conductivity type provided on the first diffusion layer and supplied with the first power supply (V pp ); A fourth diffusion layer 23 of the first conductivity type provided on the second diffusion layer 2 and supplied with the second power supply (V cc ), and a fourth diffusion layer 23 provided on the first diffusion layer 22 and the second diffusion layer 22 respectively. A fifth diffusion layer 24 and a sixth diffusion layer 24 of the first conductivity type are connected to each other and connected to the switching output terminal.
is provided between the third diffusion layer 23 and the fifth diffusion layer 24 with an insulating layer 25 interposed therebetween, and the first control signal A
A first control electrode 26 to which B is applied, and a second control electrode provided via an insulating layer 25 between the fourth diffusion layer 24 and the sixth diffusion layer 23 and to which a second control signal B is applied. 26, the first control signal A and the second control signal A
The control signal generating means for outputting the control signal B is operated by the first power supply (V pp ) or the second power supply (V cc ) having a high voltage.
この発明の電源切換回路は、第２の電源（Vcc）
より第１の電源（Vpp）の方が高電圧の場合は、
第１の電源（Vpp）が第１の制御信号Ａとなり電
源切換用FET１１を動作させ、第１の電源
（Vpp）を供給する。
The power supply switching circuit of the present invention has a second power supply (V cc ).
If the first power supply (V pp ) has a higher voltage than
The first power supply ( Vpp ) becomes the first control signal A, operates the power supply switching FET 11, and supplies the first power supply ( Vpp ).
一方、第１の電源（Vpp）より第２の電源
（Vcc）の方が高電圧の場合は、第２の電源（Vcc）
が第２の制御信号Ｂとなり電源切換用FET１２
を動作させ、第２の電源（Vcc）を供給する。 On the other hand, if the second power supply (V cc ) has a higher voltage than the first power supply (V pp ), the second power supply (V cc )
becomes the second control signal B and the power supply switching FET12
The second power source (V cc ) is supplied.
以下、この発明の一実施例を図について説明す
る。第１図において、１１，１２，１３，１４は
ＰチヤネルFET、１５，１６はｎチヤネルFET、
１７，１８はダイオードである。FET１１のソ
ースは電源（Vpp）につながり、ゲートはFET１
３のドレインとFET１５のドレインとの接点Ａ
につながり、ドレインは出力端子（Vpp／Vcc）
につながつている。FET１２のソースは電源
（Vcc）につながり、ゲートはFET１４のドレイ
ンとFET１６のドレインとの接点Ｂにつながり、
ドレインは出力端子（Vpp／Vcc）につながつて
いる。
An embodiment of the present invention will be described below with reference to the drawings. In Fig. 1, 11, 12, 13, 14 are P channel FETs, 15, 16 are N channel FETs,
17 and 18 are diodes. The source of FET11 is connected to the power supply (V pp ), and the gate is connected to FET1
Contact point A between the drain of 3 and the drain of FET15
The drain is connected to the output terminal (V pp /V cc )
connected to. The source of FET12 is connected to the power supply (V cc ), the gate is connected to contact B between the drain of FET14 and the drain of FET16,
The drain is connected to the output terminal ( Vpp / Vcc ).
ダイオード１７のアノードは電源（Vpp）につ
ながり、カソードはFET１３のソースとFET１
４のソースとの接点Ｃにつながり、ダイオード１
８のアノードは電源（Vcc）につながり、カソー
ドは接点Ｃにつながつている。 The anode of diode 17 is connected to the power supply (V pp ), and the cathode is connected to the source of FET 13 and FET 1.
Connected to contact C with the source of 4, diode 1
The anode of 8 is connected to the power supply (V cc ), and the cathode is connected to contact C.
FET１３のソースは接点Ｃにつながり、ゲー
トは接点Ｂにつながり、ドレインは接点Ａにつな
がつている。FET１４のソースは接点Ｃにつな
がり、ゲートは接点Ａにつながり、ドレインは接
点Ｂにつながつている。FET１５のドレインは
接点Ａにつながり、ゲート１２は切換信号
（PGM）が入力され、ソースは電源（Vss）につ
ながつている。 The source of FET 13 is connected to contact C, the gate is connected to contact B, and the drain is connected to contact A. The source of the FET 14 is connected to contact C, the gate is connected to contact A, and the drain is connected to contact B. The drain of the FET 15 is connected to the contact A, the gate 12 receives the switching signal (PGM), and the source is connected to the power supply (V ss ).
FET１６のドレインは接点Ｂにつながり、ゲ
ートには切換信号（PGM）を反転したものが入
力され、ソースは電源（Vss）につながつている。
FET１１，１２の基板はどこにもつながつてい
ない。FET１３，１４の基板は接点Ｃにつなが
り、FET１５，１６の基板は電源（Vss）につな
がつている。 The drain of the FET 16 is connected to contact B, the inverted switching signal (PGM) is input to the gate, and the source is connected to the power supply (V ss ).
The boards of FET11 and 12 are not connected anywhere. The substrates of FETs 13 and 14 are connected to contact C, and the substrates of FETs 15 and 16 are connected to a power supply (V ss ).
第２図はFET１，２の断面図である。P-半導
体基板２１上にN-拡散層２２を形成し、各N-拡
散層２２上にそれぞれ２個のP+拡散層２３，２
４を形成してソースおよびドレインとしている。
両P+拡散層２３，２４の間にはそれぞれ絶縁層
２５を介して制御電極２６を設けてある。 FIG. 2 is a cross-sectional view of FETs 1 and 2. An N - diffusion layer 22 is formed on a P - semiconductor substrate 21, and two P + diffusion layers 23, 2 are formed on each N - diffusion layer 22.
4 is formed to serve as a source and a drain.
A control electrode 26 is provided between both the P + diffusion layers 23 and 24 with an insulating layer 25 interposed therebetween.
上記構成において、まず、Vpp≧Vccの場合、
第２図より明らかなように、FET１１のドレイ
ンと基板間のPn接合は逆バイアスとなるので、
電源Vppと電源Vccとが短絡することはない。こ
の場合切換信号（PGM）が“Ｈ”であれば、
FET１５は導通し、接点Ａは“Ｌ”となり、
FET１１は導通する。一方、FET１６のゲート
には切換信号（PGM）の反転信号である“Ｌ”
が入つているので、FET１６は非導通となる。
FET１４のゲートは、接点Ａにつながり“Ｌ”
となつているので、FET１４は導通し、接点Ｂ
は“Ｈ”となつてFET１２は非導通となる。こ
れにより、出力端子（Vpp／Vcc）には電源電圧
Vppが出力される。これに対し、切換信号
（PGM）が“Ｌ”になると、上記のまつたく逆と
なり、接点Ａは“Ｈ”、接点Ｂは“Ｌ”となるの
でFET１１は非導通、FET１２は導通し、出力
端子（Vpp／Vcc）には電源電圧Vccが出力される。 In the above configuration, first, if V pp ≧ V cc ,
As is clear from Figure 2, the Pn junction between the drain of FET 11 and the substrate is reverse biased, so
Power supply V pp and power supply V cc are never short-circuited. In this case, if the switching signal (PGM) is “H”,
FET15 conducts, contact A becomes “L”,
FET11 becomes conductive. On the other hand, the gate of FET16 has "L" which is the inverted signal of the switching signal (PGM).
is inserted, so FET 16 becomes non-conductive.
The gate of FET14 is connected to contact A and is “L”
Therefore, FET14 is conductive and contact B
becomes "H" and the FET 12 becomes non-conductive. As a result, the power supply voltage is applied to the output terminal (V pp /V cc ).
V pp is output. On the other hand, when the switching signal (PGM) becomes "L", the above is exactly reversed, contact A becomes "H" and contact B becomes "L", so FET11 is non-conducting, FET12 is conducting, and the output Power supply voltage V cc is output to the terminal (V pp /V cc ).
次に、Vpp＜Vccの場合は、第２図よりわかる
ように、FET１２のドレインと基板間のPn接合
は逆バイアスとなるので電源Vccと電源Vppが短
絡することはない。この場合、切換信号（PGM）
が“Ｈ”であれば、FET１５は導通し接点Ａは
“Ｌ”となつてFET１１は導通する。一方、FET
１６のゲートには切換信号（PGM）の反転信号
である“Ｌ”が入つているので、FET１６は非
導通となる。FET１４のゲートは接点Ａにつな
がり“Ｌ”となつているので、FET１４は導通
し、接点Ｂは“Ｈ”となり、FET１２は非導通
となる。この結果出力端子（Vpp／Vcc）には電
源電圧Vppが出力される。これに対し、切換信号
（PGM）が“Ｌ”になると上記のまつたく逆とな
り、接点Ａは“Ｈ”、接点Ｂは“Ｌ”となるので
FET１１は非導通、FET１２は導通し、出力端
子（Vpp／Vcc）には電源電圧Vccが出力される。 Next, when V pp <V cc , as can be seen from FIG. 2, the Pn junction between the drain of the FET 12 and the substrate becomes reverse biased, so that the power supply V cc and the power supply V pp are not short-circuited. In this case, the switching signal (PGM)
If is "H", the FET 15 is conductive, the contact A is "L", and the FET 11 is conductive. On the other hand, FET
Since "L", which is an inverted signal of the switching signal (PGM), is input to the gate of FET 16, FET 16 becomes non-conductive. Since the gate of FET 14 is connected to contact A and is at "L", FET 14 is conductive, contact B is at "H", and FET 12 is non-conductive. As a result, the power supply voltage Vpp is output to the output terminal ( Vpp / Vcc ). On the other hand, when the switching signal (PGM) becomes "L", the above is exactly the opposite, and contact A becomes "H" and contact B becomes "L".
The FET 11 is non-conductive, the FET 12 is conductive, and the power supply voltage V cc is output to the output terminal (V pp /V cc ).
なお、上記実施例では、電源切換のための
FET１１，１２としてＰチヤネルFETを使用し
ているが、第３図のように構成すればｎチヤネル
FETを使用することもできる。すなわち、第３
図において、３１〜３４はＮチヤネルFET、３
５，３６はＰチヤネルFETである。電源切換用
ＮチヤネルFET３１，３２は第２図において各
部の導電形を逆にすることにより形成される。 In addition, in the above embodiment, the
P-channel FETs are used as FETs 11 and 12, but if configured as shown in Figure 3, N-channel FETs are used.
FETs can also be used. That is, the third
In the figure, 31 to 34 are N-channel FETs, 3
5 and 36 are P channel FETs. The power supply switching N-channel FETs 31 and 32 are formed by reversing the conductivity type of each part in FIG.
以上のように、この発明によれば、電源切換用
FETの基板電位をソースまたはドレインを通し
て与える構成としたので、両電源電圧の大小関係
にかかわらず、電源間が短絡するようなことはな
くなり、電源電圧の大小関係に制限を設ける必要
がなくなつた。
As described above, according to the present invention,
Since the substrate potential of the FET is applied through the source or drain, there will be no short circuit between the power supplies regardless of the magnitude relationship between the two power supply voltages, and there is no need to place restrictions on the magnitude relationship of the power supply voltages. .
第１図は本発明の一実施例を示す回路図、第２
図はその電源切換用FETの構成を示す断面図、
第３図は本発明の他の実施例を示す回路図、第４
図は従来例を示す回路図、第５図はその電源切換
用FETの構成を示す断面図である。
１１，１２……ＰチヤネルFET、３１，３２
……ＮチヤネルFET、２１……P-基板、２２…
…N-拡散層、２３，２４……P+拡散層、２５…
…絶縁層、２６……制御電極。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a cross-sectional view showing the configuration of the power switching FET,
FIG. 3 is a circuit diagram showing another embodiment of the present invention;
The figure is a circuit diagram showing a conventional example, and FIG. 5 is a sectional view showing the configuration of the power supply switching FET. 11, 12...P channel FET, 31, 32
...N-channel FET, 21...P - board, 22...
...N - diffusion layer, 23, 24...P + diffusion layer, 25...
...Insulating layer, 26...Control electrode.
Claims (1)
導電型の第１の拡散層と第２の拡散層と、 前記第１の拡散層上に設けられ第１の電源が供
給される第１導電型の第３の拡散層と、 前記第２の拡散層上に設けられ第２の電源が供
給される第１導電型の第４の拡散層と、 前記第１の拡散層と第２の拡散層にそれぞれ設
けられ、互いに切り換え出力端子に接続されてい
る第１導電型の第５の拡散層と第６の拡散層と、 前記第３の拡散層と第５の拡散層の間に絶縁層
を介して設けられ、第１の制御信号が印加する第
１の制御電極と、 前記第４の拡散層と第６の拡散層の間に絶縁層
を介して設けられ、第２の制御信号が印加する第
２の制御電極とを有し、 前記第１の制御信号と第２の制御信号を出力す
る制御信号発生手段が、前記第１の電源か第２の
電源の電圧の高い電源により動作することを特徴
とする電源切換回路。[Claims] 1. A second semiconductor substrate provided on a semiconductor substrate of a first conductivity type.
a first diffusion layer and a second diffusion layer of conductivity type; a third diffusion layer of first conductivity type provided on the first diffusion layer and supplied with a first power source; and a third diffusion layer of the first conductivity type. a fourth diffusion layer of the first conductivity type provided on the diffusion layer and supplied with a second power source; and a fourth diffusion layer of the first conductivity type provided on the first diffusion layer and the second diffusion layer, each of which is connected to a switching output terminal. a fifth diffusion layer and a sixth diffusion layer of a first conductivity type, and an insulating layer is provided between the third diffusion layer and the fifth diffusion layer, and a first control signal is applied. a second control electrode provided between the fourth diffusion layer and the sixth diffusion layer with an insulating layer interposed therebetween, and to which a second control signal is applied; A power supply switching circuit characterized in that the control signal generating means for outputting the first control signal and the second control signal is operated by a power supply having a high voltage of the first power supply or the second power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60266702A JPS62124700A (en) | 1985-11-25 | 1985-11-25 | Power source switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60266702A JPS62124700A (en) | 1985-11-25 | 1985-11-25 | Power source switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62124700A JPS62124700A (en) | 1987-06-05 |
| JPH0529997B2 true JPH0529997B2 (en) | 1993-05-06 |
Family
ID=17434494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60266702A Granted JPS62124700A (en) | 1985-11-25 | 1985-11-25 | Power source switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62124700A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1232973B (en) * | 1987-12-01 | 1992-03-11 | Sgs Microelettronica Spa | VOLTAGE POWER SWITCHING DEVICE FOR NON-VOLATILE MEMORIES IN MOS TECHNOLOGY |
| JP2733796B2 (en) * | 1990-02-13 | 1998-03-30 | セイコーインスツルメンツ株式会社 | Switch circuit |
| JP2672740B2 (en) * | 1991-10-07 | 1997-11-05 | 三菱電機株式会社 | Microcomputer |
| JP2001156619A (en) * | 1999-11-25 | 2001-06-08 | Texas Instr Japan Ltd | Semiconductor circuit |
| DE10006517A1 (en) * | 2000-02-15 | 2001-08-23 | Infineon Technologies Ag | Circuit arrangement for discharging a capacitance charged to a high voltage to a low voltage controlled by means of a control unit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114396A (en) * | 1981-12-26 | 1983-07-07 | Toshiba Corp | Nonvolatile memory |
-
1985
- 1985-11-25 JP JP60266702A patent/JPS62124700A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114396A (en) * | 1981-12-26 | 1983-07-07 | Toshiba Corp | Nonvolatile memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62124700A (en) | 1987-06-05 |
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