JPS6392093A - Manufacture of multilayer interconnection board - Google Patents

Manufacture of multilayer interconnection board

Info

Publication number
JPS6392093A
JPS6392093A JP23732586A JP23732586A JPS6392093A JP S6392093 A JPS6392093 A JP S6392093A JP 23732586 A JP23732586 A JP 23732586A JP 23732586 A JP23732586 A JP 23732586A JP S6392093 A JPS6392093 A JP S6392093A
Authority
JP
Japan
Prior art keywords
hole
outer layer
holes
inner layer
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23732586A
Other languages
Japanese (ja)
Inventor
芝原 優
比嘉 一智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23732586A priority Critical patent/JPS6392093A/en
Publication of JPS6392093A publication Critical patent/JPS6392093A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はIC,LSI等の機能素子の集積度アップとと
もに配線板の多層化が必要であるコンピュータ分野等の
精密電子機器に用いることができる多層配線板の製造方
法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to multilayer wiring that can be used in precision electronic equipment such as computers, which requires increased integration of functional elements such as ICs and LSIs, and multilayer wiring boards. This invention relates to a method for manufacturing a board.

従来の技術 一般に多層配線板用内層回路の形成方法とじては、薄い
銅張積層板にスクリーン印刷性又は写真法にて工、ソテ
ングレジストを形成し、エツチング液をスプレーして、
エツチングを行い内層回路を形成してきた。
2. Description of the Related Art In general, the method for forming inner layer circuits for multilayer wiring boards is to form a saturation resist on a thin copper-clad laminate using screen printing or photography, and then spraying an etching solution.
Etching has been performed to form inner layer circuits.

発明が解決しようとする問題点 上記方法によるものは回路形成過程にて、内層用のフィ
ルムを使用するため、温度や湿度の影響で保管中又は運
送中に寸法が狂って内層ショートの原因となる。内層回
路のショートは修正がほとんど不可能で多層配線板にと
っては致命的欠陥である。又、エツチング液には、塩化
第2銅、塩化第2鉄、膜剥離液には苛性ソーダ等のアル
カリ溶液、有機溶剤が使用されており、取扱い時の危険
性、公害処理等の面で問題がある。
Problems to be Solved by the Invention Since the above method uses a film for the inner layer during the circuit formation process, the dimensions may be distorted during storage or transportation due to the influence of temperature and humidity, causing inner layer short circuits. . Short circuits in inner layer circuits are almost impossible to correct and are a fatal defect for multilayer wiring boards. In addition, the etching solution uses cupric chloride and ferric chloride, and the film stripping solution uses alkaline solutions such as caustic soda and organic solvents, which pose problems in terms of handling hazards and pollution treatment. be.

本発明は上記のような従来の欠点を除去するものであり
、内層回路のショートの危険性を排除した加工精度の安
定な多層配線板の製造方法を提供するものでちる。
The present invention eliminates the above-mentioned conventional drawbacks and provides a method for manufacturing a multilayer wiring board with stable processing accuracy and eliminating the risk of short circuits in inner layer circuits.

問題点を解決するだめの手段 上記問題点を解決するために本発明は片面に金属箔を貼
付した薄い絶縁基板の外層回路と導通の必要のあるスル
ホール部は孔明けをせず、外層回路と絶縁の確保が必要
なスルホール部は金型によるプレス、又はNCドリル等
エスルホール孔より大きく孔明けをし、内層の電源回路
層、ンールド回路層を形成する方法としだものである。
Means for Solving the Problems In order to solve the above problems, the present invention is a thin insulating substrate with metal foil pasted on one side, and the through-holes that need to be connected to the outer layer circuits are not drilled and are connected to the outer layer circuits. The most common method for forming the through-hole portion where insulation is required is to press with a mold or drill a hole larger than the through-hole hole using an NC drill to form the inner power supply circuit layer and rolled circuit layer.

作用 上記方法とすることにより温度や湿度の影響を受けず寸
法が狂わない。内層回路の寸法ズレによる内層ショート
が皆無となり、加工精度の安定した多層配線板の歩留向
上が図れるものとなる。
Effect: By using the above method, the dimensions are not affected by temperature or humidity and the dimensions do not go out of order. There is no inner layer short circuit due to dimensional deviation of the inner layer circuit, and the yield of multilayer wiring boards with stable processing accuracy can be improved.

実施例 以下本発明の一実施例である4層多層配線板の製造方法
を図面を参照して説明する。
EXAMPLE Hereinafter, a method for manufacturing a four-layer multilayer wiring board, which is an example of the present invention, will be explained with reference to the drawings.

第2図、第3図は極薄のエポキンガラス絶縁材1.2に
35μ内層銅箔3,4を貼付したものの断面図である。
FIGS. 2 and 3 are cross-sectional views of an extremely thin Epoquine glass insulating material 1.2 with 35μ inner layer copper foils 3, 4 attached.

第4図、第5図は上記第2図、第3図の内層銅箔3.4
を貼付したエポキシガラスPR材1.2の外層導体と絶
縁の必要のあるスルホール部に金型によるプレス、又は
、NCドリルによシスルホール孔より大きく孔明けした
断面図である。5′/′i外層回路と絶縁の確保の必要
なスルホール部、6は外層回路と導電の必要のあるスル
ホール部である。
Figures 4 and 5 are the inner layer copper foil 3.4 of Figures 2 and 3 above.
It is a sectional view in which a hole larger than the thistle hole is drilled by pressing with a mold or by an NC drill in a through-hole portion that needs to be insulated from the outer layer conductor of the epoxy glass PR material 1.2 to which is pasted. 5'/'i is a through-hole part that needs to be insulated from the outer layer circuit, and 6 is a through-hole part that needs to be electrically conductive with the outer layer circuit.

第6図は上記孔明は加工を施した絶縁材1,2の積層し
た状態を示した断面図である。尚、第4図、第5図の内
層用回路は、図のごとく、表、裏の状態に設置する。7
は内層銅箔3と外層銅箔8を接着する接着シートである
。この接着シート7は、加圧(15〜5okg/c7J
)、加温(170°c程度)1時間(40〜80分程度
)によって流動、固化し、外層回路と絶縁の確保の必要
のあるスルホール部6の孔明けした孔を接着シート7の
樹脂で埋めることができる。9は積層用熱盤である。
FIG. 6 is a sectional view showing a laminated state of the insulating materials 1 and 2 which have been subjected to the above-mentioned hole processing. The inner layer circuits shown in FIGS. 4 and 5 are installed on the front and back sides as shown. 7
is an adhesive sheet for bonding the inner layer copper foil 3 and the outer layer copper foil 8. This adhesive sheet 7 is pressurized (15~5okg/c7J
), heated (approximately 170°C) for 1 hour (approximately 40 to 80 minutes) to flow and solidify, and the resin of the adhesive sheet 7 is used to fill the holes of the through-hole portions 6 that need to ensure insulation with the outer layer circuit. can be filled. 9 is a heating plate for lamination.

第7図は、積層した後、外層回路と絶縁の確保の必要の
あるスルホール部5の孔明した孔を接着シート7の樹脂
で埋めた図である。
FIG. 7 is a diagram in which the holes formed in the through-hole portions 5, which need to ensure insulation from the outer layer circuit, are filled with the resin of the adhesive sheet 7 after lamination.

第8図はスルホール孔10の孔加工した断面図である。FIG. 8 is a cross-sectional view of the through-hole hole 10.

第9図はスルホールメッキ11を施しだ断面図である。FIG. 9 is a sectional view showing through-hole plating 11 applied.

スルホール部5は外層銅箔8と絶縁性を確保でき、スル
ホール部4は外層銅箔8と導通性が得られている。
The through hole portion 5 can ensure insulation with the outer layer copper foil 8, and the through hole portion 4 can have electrical conductivity with the outer layer copper foil 8.

第10図はメソキレシスト印刷12を施した断面図であ
る。
FIG. 10 is a cross-sectional view after mesochyresist printing 12 has been applied.

第11図はエツチングレジストメッキ13を施した断面
図である。
FIG. 11 is a cross-sectional view showing the etching resist plating 13 applied.

第1図は苛性ソーダ等で膜剥離、エツチングした多層配
線板の完成品の断面図であり、外層、内層の回路形成は
完成する。
FIG. 1 is a cross-sectional view of a completed multilayer wiring board that has been peeled off and etched using caustic soda or the like, and circuit formation on the outer and inner layers has been completed.

発明の効果 以上のように本発明は、多層配線板の製造方法として金
型によるプレス、又はNCドリルで孔明けし、内層回路
を形成しているので、スクリーン印刷法、写真法による
フィルムを利用して内層回路を形成する方法よりも、温
度や湿度等の環境の影響を受けず寸法精度の安定した多
層配線板用内層回路が形成できるだめ、内層回路の寸法
ズレによる内層ショートが皆無となり、歩留の向上が図
れると共に信頼性の高いコンピュータ分野等の精密電子
機器に寄与する。塩化第2銅、塩化第2鉄等の工1.テ
ンダ液、苛性ンーダ、有機溶剤等の膜剥離液を使用する
必要がなく、公害処理の面で有利となるなどの効果をも
ち工業価値の犬なるものである。
Effects of the Invention As described above, the present invention is a method for manufacturing a multilayer wiring board, in which inner layer circuits are formed by pressing with a mold or by drilling holes with an NC drill, so film produced by screen printing or photography is used. It is possible to form inner layer circuits for multilayer wiring boards with stable dimensional accuracy without being affected by the environment such as temperature and humidity than with the method of forming inner layer circuits using a method of forming inner layer circuits. It can improve yield and contribute to highly reliable precision electronic equipment such as in the computer field. Processing of cupric chloride, ferric chloride, etc. 1. It does not require the use of membrane stripping liquids such as tender liquid, caustic powder, and organic solvents, and is advantageous in terms of pollution treatment, making it an industrial value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の多層配線板の製造方法の一実施例によ
り得だ多層配線板の断面図、第2図〜第11図は本発明
の一実施例の4層多層配線板の内層回路形成方法におけ
る各工程の断面図である。 1.2・・・・・・極薄エボキンガラス絶縁材、3,4
・・・・・・内層銅箔、5・・・・・・外層回路と絶縁
の確保の必要なスルホール部、6・・・・・・外層回路
と導電の必要なスルホール部、7・・・・・・接着シー
ト、8・・・・・・外層銅箔、9・・・・・・積層用熱
盤、10・・・・・スルホール孔、11・・・・・・ス
ルホールメッキ、12・・・・・・メソキレシスト印刷
、13・・・・・・エツチングレジストメッキ。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第9
図 lθ
FIG. 1 is a sectional view of a multilayer wiring board obtained by an embodiment of the method for manufacturing a multilayer wiring board of the present invention, and FIGS. 2 to 11 are inner layer circuits of a four-layer multilayer wiring board of an embodiment of the invention. It is sectional drawing of each process in a formation method. 1.2... Ultra-thin Evokin glass insulation material, 3,4
...Inner layer copper foil, 5...Through-hole part that requires insulation from the outer layer circuit, 6...Through-hole part that requires conductivity from the outer layer circuit, 7... ...Adhesive sheet, 8...Outer layer copper foil, 9...Hot plate for lamination, 10...Through hole hole, 11...Through hole plating, 12... ... Mesochresist printing, 13... Etching resist plating. Name of agent: Patent attorney Toshio Nakao and one other person No. 9
Figure lθ

Claims (1)

【特許請求の範囲】[Claims]  片面に金属箔を貼付した薄い絶縁材の外層回路と導通
の必要のあるスルホール部は孔明けをせず、外層回路と
絶縁の確保が必要なスルホール部は、金型によるプレス
、NCドリル等でスルホール孔より大きく孔明けし、こ
れを外層金属箔とともに接着シートを介して積層し、ス
ルホール孔を形成してスルホールメッキを施すとともに
外層回路を形成する多層配線板の製造方法。
The through-holes that require continuity with the outer layer circuit of a thin insulating material with metal foil pasted on one side are not drilled, and the through-holes that require insulation from the outer layer circuit are pressed with a mold, NC drill, etc. A method for manufacturing a multilayer wiring board, in which a hole is made larger than the through-hole hole, the holes are laminated together with an outer layer metal foil via an adhesive sheet, through-hole holes are formed, through-hole plating is applied, and an outer layer circuit is formed.
JP23732586A 1986-10-06 1986-10-06 Manufacture of multilayer interconnection board Pending JPS6392093A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23732586A JPS6392093A (en) 1986-10-06 1986-10-06 Manufacture of multilayer interconnection board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23732586A JPS6392093A (en) 1986-10-06 1986-10-06 Manufacture of multilayer interconnection board

Publications (1)

Publication Number Publication Date
JPS6392093A true JPS6392093A (en) 1988-04-22

Family

ID=17013698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23732586A Pending JPS6392093A (en) 1986-10-06 1986-10-06 Manufacture of multilayer interconnection board

Country Status (1)

Country Link
JP (1) JPS6392093A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211897A (en) * 1990-01-17 1991-09-17 Tanaka Kikinzoku Kogyo Kk Manufacture of multilayer blind through hole printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211897A (en) * 1990-01-17 1991-09-17 Tanaka Kikinzoku Kogyo Kk Manufacture of multilayer blind through hole printed circuit board

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