JPS6389128U - - Google Patents

Info

Publication number
JPS6389128U
JPS6389128U JP18530786U JP18530786U JPS6389128U JP S6389128 U JPS6389128 U JP S6389128U JP 18530786 U JP18530786 U JP 18530786U JP 18530786 U JP18530786 U JP 18530786U JP S6389128 U JPS6389128 U JP S6389128U
Authority
JP
Japan
Prior art keywords
interface
scanner
interface circuit
printer
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18530786U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18530786U priority Critical patent/JPS6389128U/ja
Publication of JPS6389128U publication Critical patent/JPS6389128U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の要部であるスキヤ
ナ・プリンタ・インタフエースの詳細な構成を示
す図、第2図は実施例のシステム構成を示す図、
第3図は他の実施例を示す構成図、第4図は従来
のシステムの構成例を示す図である。 1:CPU、2:メモリ、3:スキヤナインタ
フエース、3A:スキヤナ・プリンタ・インタフ
エース、4:プリンタインタフエース、5:スキ
ヤナ、6:プリンタ、7:システムバス。
FIG. 1 is a diagram showing the detailed configuration of a scanner printer interface, which is the main part of an embodiment of the present invention, and FIG. 2 is a diagram showing the system configuration of the embodiment.
FIG. 3 is a configuration diagram showing another embodiment, and FIG. 4 is a diagram showing an example of the configuration of a conventional system. 1: CPU, 2: Memory, 3: Scanner interface, 3A: Scanner/printer interface, 4: Printer interface, 5: Scanner, 6: Printer, 7: System bus.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部のシステムバスとスキヤナおよびプリンタ
との間のデータ転送を行うインタフエース回路に
おいて、イメージスキヤナ・インタフエースとビ
ツトマツプ・インタフエースとバスインタフエー
スとをバツフアメモリを介して接続する如く構成
したことを特徴とするインタフエース回路。
In an interface circuit that transfers data between an external system bus, a scanner, and a printer, an image scanner interface, a bitmap interface, and a bus interface are configured to be connected via a buffer memory. interface circuit.
JP18530786U 1986-12-01 1986-12-01 Pending JPS6389128U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18530786U JPS6389128U (en) 1986-12-01 1986-12-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18530786U JPS6389128U (en) 1986-12-01 1986-12-01

Publications (1)

Publication Number Publication Date
JPS6389128U true JPS6389128U (en) 1988-06-10

Family

ID=31133810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18530786U Pending JPS6389128U (en) 1986-12-01 1986-12-01

Country Status (1)

Country Link
JP (1) JPS6389128U (en)

Similar Documents

Publication Publication Date Title
JPS6389128U (en)
JPS5980505U (en) temporary bridge
JPS62166558U (en)
JPS6446862U (en)
JPH0466625U (en)
JPH0186543U (en)
JPS5890405U (en) I/O auxiliary device for sequencer
JPS62162756U (en)
JPS60164236U (en) programmable controller
JPS61103750U (en)
JPH0365338U (en)
JPS58142734U (en) Address generation circuit for bus-coupled system
JPS6392971U (en)
JPH0218123U (en)
JPS6339754U (en)
JPS63155549U (en)
JPS5847929U (en) Bus contention prevention circuit
JPS6327952U (en)
JPS6316323U (en)
JPS62201558U (en)
JPS62112742U (en)
JPS6353151U (en)
JPS635542U (en)
JPS6380670U (en)
JPH01106949U (en)