JPS638587A - Integrated circuit with testing function - Google Patents

Abstract

PURPOSE:To achieve a testing of a function circuit without use of a special test terminal, by supplying a clock pulse for testing to an alarm terminal to reset a desired frequency dividing stage while a clock pulse is supplied to the function circuit. CONSTITUTION:When testing a function circuit, first, an alarm terminal 6 normally set to '0' is set to '1' and then, a clock pulse is supplied thereto. When pulse from an output Q3 of a frequency dividing stage 3 does not fall with at the pulse state at 0, outputs Q and -Q of an FF circuit 7 are held at 1 and 0 respectively to generate an alarm signal from an alarm control circuit 5 while a clock pulse passes through a gage circuit 9. Then, a clock pulse passes through a gate circuit 10 to reset a frequency dividing stage 2 while passing through a gate circuit 11 to be supplied to the frequency dividing stage 3. Thus, a driving circuit 4 is tested, too.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an integrated circuit with a test function.

[Prior Art] For example, integrated circuits for quartz watches require high precision and reliability. Therefore, during manufacturing, it is necessary to test each integrated circuit to determine whether the frequency dividing circuit operates normally, and the time required for this test becomes a major problem.

Conventionally, in order to perform this test, a test terminal is provided on the integrated circuit, and a high-speed external clock pulse for testing is supplied from this terminal to an intermediate stage of the frequency dividing circuit. During this test, it is necessary to stop the previous frequency dividing stage, so in addition to the test terminals described above, a stop terminal was also provided.

[Problems to be Solved by the Invention] Conventional devices require test and stop terminals, which increases the chip size of the integrated circuit, leading to an increase in cost.

The present invention provides an integrated circuit with a test function that allows testing of a functional circuit without adding a terminal exclusively for testing.

[Means for solving the problem] The present invention resets a desired frequency division stage by supplying a test clock pulse to an alarm terminal from the outside, and also supplies the test clock pulse to a functional circuit to perform a test. This is what I decided to do.

[Embodiment] In FIG. 1, 1 is an oscillator, 2 and 3 are frequency dividing stages, and 4 is a motor drive circuit. This drive circuit 4 and frequency division stage 3
constitutes the functional circuit to be tested. 5 is an alarm control circuit which generates an alarm signal while its input terminal is "1". 6 is an alarm terminal, 7,
8 is a flip-flop circuit, and 9, 10, and 11 are gate circuits.

In the above configuration, under normal conditions, the alarm terminal 6 is “0”.
”, and the output Q of the flip-flop circuit 7 is “
Therefore, the alarm control circuit 5
is held in an inactive state, the outputs of gate circuits 9 and 10 are held at 0'', frequency dividing stage 2 is operated, and the output from frequency dividing stage 3 causes drive circuit 4 to generate driving pulses for the motor.

Then, at the alarm time, the alarm switch operates and the second
When the alarm terminal 6 becomes "1" as shown in Figure AI, the subsequent fall of the output from the output Q3 of the frequency dividing stage 3 (Figure 2 F
3), the outputs Q and Q of the flip-flop circuit 7 are
become 1' and "0" as shown in FIG. 2, P and P, respectively, and the alarm control circuit 5 operates to generate an alarm signal.

On the other hand, the output of the gate circuit 9 becomes 1'' as shown in Fig. 2 P, but the output Q of the flip-flop circuit 8 becomes 1'' as shown in Fig. 2 PH.
The gate circuit 1 remains held at “0” as shown in FIG.
The output of 0 is held at 10'' as shown in Fig. 2 Pr. Therefore, the operation of the frequency dividing stage 2.3 is maintained as it is.

When the ringing is stopped, the alarm terminal 6 is inverted to "0°", the output of the gate circuit 9 is inverted to "O" as shown in FIG. 2 Pc, and the output Q of the flip-flop circuit 8 is inverted to "0" as shown in FIG. However, at this time, the gate circuit 10
is closed, so the output of the gate circuit 10 remains held at "0". Thereafter, due to the fall of the output Q3 of the frequency dividing stage 3, the output Q from the flip-flop circuit 7,
Q is "0" as shown in Figure 2, P and P, respectively.

R Inverted to “1”. Therefore, the alarm signal from the alarm control circuit 5 stops and the alarm sound stops. Furthermore, the flip-flop circuit 8 is reset and returns to the normal state.

Next, the test operation will be explained. In this case, after setting the alarm terminal 6 to ``1'', a test clock pulse is supplied as shown in FIG. If the pulse does not fall, the outputs Q and Q of the flip-flop circuit 7 are held at "1" and "0", respectively, and the alarm control circuit 5 generates an alarm signal, and the gate circuit 9 passes the clock pulse. . This clock pulse causes the output Q of the flip-flop circuit 8 to become “
1". Therefore, the above clock pulse is held at the third
As shown in FIG. Pr, the signal passes through a gate circuit 10, further passes through a gate circuit 11, and is supplied to the frequency dividing stage 3.

On the other hand, the clock pulse is supplied to the reset terminal of the frequency dividing stage 2 and reset is applied. By setting the pulse width of the ``0 level'' of the bipedal clock pulse to be shorter than 1/2 of the pulse width of the output pulse from frequency dividing stage 2,
Regardless of the frequency of the clock pulse, no output is generated from the frequency dividing stage 2.

Therefore, the frequency divider stage 3 and the drive circuit 4 are tested by the clock pulses.

Further, the output Q of the flip-flop circuit 7 activates the alarm system 1, and its test is also performed at the same time.

In the above embodiment, the case where the frequency dividing stage and the motor drive circuit were tested as functional circuits was explained.
The present invention is not limited to this, and for example, a snooze counter or the like may be tested.

[Effects of the Invention] According to the present invention, a desired frequency division stage is reset by supplying a test clock pulse to an alarm terminal, and the clock pulse is supplied to a functional circuit, so that a dedicated test terminal is not required. It is possible to test functional circuits without the need for an integrated circuit, and the chip size of the integrated circuit can be small, leading to cost reductions.

In particular, when testing a frequency division stage as a functional circuit, test clock pulses can be supplied from an intermediate stage of the frequency division stage.
This allows for high-speed testing.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are time charts for explaining the operation. 2.3... Frequency division stage 4... Drive circuit 5... Alarm control circuit 6... Alarm terminal 7.8... Flip-flop circuit 9.10.11... Gate circuit. 1 Figure 21.4 PT□

Claims (1)

[Claims] A frequency dividing circuit that divides the reference frequency signal, a functional circuit that operates in response to the output from this frequency dividing circuit, an alarm terminal that reaches a desired potential level by the operation of an alarm switch, and this alarm terminal that operates at the desired potential level. an alarm control circuit that generates an alarm signal when the potential level is reached; and a test clock pulse that is supplied to the alarm terminal to reset a desired frequency dividing stage of the frequency divider circuit, and also causes the functional circuit to perform the test. An integrated circuit with a test function, consisting of a control circuit that supplies clock pulses for the test.