JPS58154688A - Integrated circuit for electronic watch - Google Patents

Abstract

PURPOSE:To perform tests without the preparation of any test terminal and shorten test time, by using an existing terminal as a test terminal and providing the titled circuit with a circuit to specify the test mode. CONSTITUTION:An intermediate level signal impressed to the 1st terminal to which an alarm coincident signal or the like is to be impressed is detected by a three level value detecting circuit 6 and a signal to prepare the initial state of the test mode is generated. An alarm signal or the like formed by the 1st terminal and a frequency division output from a frequency dividing circuit is outputted. A test mode selecting circuit 10 sets up the test mode by the signal input to the 2nd terminal. Plural outputs from the selecting circuit 10 specify the test mode of plural gates. When the outputs of the selecting circuit 10 specify two gates simultaneously, a prescribed level signal is applied to any one of the 1st and 2nd terminals and a test pulse is impressed to the other terminal, so that the test pulse is applied to the prescribed internal circuit through the gate specified by the prescribed level signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit for an electronic time hand, and particularly to an integrated circuit for an electronic time hand that has an alarm function and is capable of testing an internal circuit using an alarm input terminal and an alarm output terminal. Regarding.

Generally, electronic watches using a step motor that have an alarm function mechanically detect coincidence of alarms and apply an alarm coincidence signal to an alarm input terminal to perform an alarm operation.

The integrated circuit used in such analog display electronic clocks has a terminal to connect the crystal oscillator, a terminal to drive the step motor, a terminal to which the alarm matching signal is applied, and an alarm signal output to generate the alarm sound. It has the advantage of being able to be configured with a small number of terminals. However, in conventional integrated circuits, test terminals are provided for adjusting the oscillation frequency and testing internal circuits, and when adding a snooze function, four snooze terminals must be provided. ,
The advantage of being able to configure the structure with a small number of terminals is lost, and the test time also becomes longer due to the increase in Wj&ability.

The present invention has been made in view of the above-mentioned points, and relies on sharing the test terminal with the m terminal and providing a circuit for specifying the test mode. The present invention provides an integrated circuit for an electronic watch that can shorten test time. The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, which is an integrated circuit for an analog chisel clock with an alarm and snooze function using a step motor.

(1) is the oscillation circuit, +21 +31 f4+' +5
1 is the first, second, and so on. @3 and 4th frequency divider circuits, (6) is a three-value detection circuit, (7) is an alarm and snooze set pulse generation circuit, 7 lip-flops for storing 8-digit alarms, (9) is snooze memory Nori, Buflop, ALI
N is an alarm input terminal which is the first terminal, LO is an alarm output terminal which outputs an alarm signal to sound an alarm, VO is a test mode selection circuit, and QXl is a test pulse generation circuit.

The oscillation circuit il+ consists of an inverter and a feedback resistor 1, and a crystal oscillator (
) generates a reference signal of 4.194.304 Hz, the output of which is applied to the input of the first frequency divider circuit (2). 1st, 2nd and 6th frequency dividing circuit t21 +3)
+41 has a total of 23 stages of T-FFs connected continuously, and between the first frequency dividing circuit 2 and the second frequency dividing circuit (3), that is, between the 11th stage and the 12th stage. is inverter a4
and a NAND gate (to), and between the second division circuit (3) and the sixth frequency division circuit (4), that is, 16
A NAND gate and an inverter are also interposed between the 17th stage and the 17th stage.

The final output Qll of the first frequency divider circuit (2) is 2048Hz
The output Q1g of the second frequency dividing circuit (3) is 64 Hz%
The output Q23 of the frequency dividing circuit (1) is 2 Hz. Divided output Q18, Q20s of the third frequency divider circuit (4)
Q21% Q22 is applied to the NAND gate (to),
NAND gate (2) is applied to the divided-by-9 output;
A short pulse of 9 seconds is generated once per second, and SO is applied to the NOR gate asci1 and the NAND gate (2). The branch output Q23 is applied to the NOR gate, while the branch output Q23 inverted by the inverter is applied to the NOR gate. NOR gate (2)■
are alternately conductive, so output terminals 0UT1 and 0UT2 are connected to inverter c13cj4 and inverter @(2), respectively.
) t-, the seconds signal SO is output alternately. A step motor is connected to the output terminals 0UT1 and 0UT2, and is driven depending on the second boar SO. What inverter (goods) (to) is the driver of the step motor.

The fourth frequency dividing circuit 151 to which the second signal SO is applied via the NAND gate and the inverter is a T-FF.
It consists of 9 stages of continuous connection, and measures the alarm time and snooze time.

The three-value detection circuit (6) is composed of an inverter @(2)...(2) and an AND gate (to), and the inverter (2)
(to) is the first terminal, the alarm input terminal ALIN.
are connected, and the output of the AND game 11 is connected to the number AL
It is output as M, ALH. The inverters @4 have different threshold levels, and the threshold level VT2 of the remote inverter (2) is made larger than the threshold level VTI of the inverter (2). Normally, the alarm input terminal ALIN depends on the resistor R2.
, 0 which is at VDD level, that is, V T 1 <”
In the case of V T 2 < A L I N, both inverters (2) and - are turned on and their outputs are set to 0. Therefore, the 11! number ALH is set to 11" and the signal ALM is set to It has become. Furthermore, when a signal of VT 1 <AτIN < VT2 is applied, the inverter cmri turns on and outputs C10'', and the inverter @ turns off and outputs ``1'', so the signal ALH becomes @0'' and the polarization ALM Then, when the ALIN<VT1<VT2 signals are applied, both inverters cS (support) turn off and their output becomes @1'', so the signal ALH and signal ALM both become @0. '. For example, if VDD is 15V and the gi Ar〒 ball changes within the range of 1.5V to 0, then VTI is 0.65V, VT2 is Q, and 85V is selected for Neto. It will be done.

Normally, an alarm coincidence detection switch and a snooze switch are connected in series between the alarm input terminal ALIN and the ground level, and when the set alarm time arrives, the alarm coincidence detection switch closes and the alarm input terminal ALIN
is forcibly set to '0'', and in order to enter the snooze free mode, 1. In the alarm state, open and close the snooze switch within a certain period of time, and input 10''-11''-@0'' to the alarm input terminal ALIN. Apply signal. These I
As a change in the output ALH of the No. N three-value detection circuit (6),
Used for alarm and snooze control.

The set pulse generation circuit (7) detects the rise of the signal ALH and the rise of the signal F, and generates set pulses PU1 and P.
It outputs UZ, inverter, D-FF can (to), NAND gate □□□ and N0 gate (to)
It consists of The output Q18 of the sixth frequency dividing circuit (4) is applied to the clock input of the D-FF (to), and the rising edge of the signal ALH is connected to the output terminal of the I)-FF circuit and the D-
It is detected by the NOR gate which inputs the output Q of FF (to), and the pulse width of -f1M of the divided output Q18 is '
1” is output (Rus PU2 is output, and
The rising edge of the signal ALH is the signal A L HID-FF
(to) output Q%D - FF (to) output Q and frequency division output Qls are detected by NAND gate (2) as inputs, and @0 with a pulse width equal to the pulse width of frequency division output Q18
'',) Noculus PU1 explodes in output 〇 Set pulse PU2 is alarm flip frog (8)
is set, and the NOR gate (to) and N
Through the AND circuit, the fourth frequency dividing circuit (5) is reset, and the set pulse PU1 is set to VcN A N.
D gate l! 11'1, the fourth frequency divider circuit (5
) to reset.

Here, the alarm operation and snooze operation will be explained.

If the set alarm time is not set, alarm input terminal ALI
When N becomes °0", signal ALH changes from @1'" to @0"
stand down. The alarm flip-flop (8) is triggered by the set pulse PU2 output at this time.

- The power snooze flip frog (9) is in the reset state suddenly, the signal is 8Nt'i''O1'', and the output Q of the D-FF plane is @0', so the NOR Kate Co., Ltd. alarm control signal Let ALS be °1''.The AND gate to which the alarm control signal ALS is applied is the divided output Q.
22, QlG is applied, creating an alarm intermittent signal and applying it to the NAND gate via the OR gate. A branch output Qo with a frequency of 2048 Hz is applied to the NAND gate, superimposed on the intermittent alarm signal, and outputted to the alarm output terminal ALOK via an inverter.

On the other hand, the reset m4 frequency dividing circuit (5) restarts the needle wall of the second signal, and after a certain period of time, 128 seconds, the output Qao becomes "1". At this time, the output SN of the flip-flop opening 7 (9) in the reset 7-shaped candy is 111, so the output Q30 is output from the alarm flip-flop (8) via the AND gate. Gate■
is shut off by the output of the alarm flip-flop (8-), the alarm brake No. 1d AL8 becomes 10'', and the alarm stops.

Snoo
When it becomes ``1'', the 1g A L H rises to 10°-1'', and at this time, the NAND gate (support) outputs the set pulse PU1, and the snooze 7 lip 70 knob (9) is set. In addition, the fourth frequency dividing circuit U3+
is reset. Since the snooze 7 reset flag (9) is set, the object number SN becomes "1", and the output Q of D-FFJI is also ``1'', so NO
1't gate tune causes the alarm control signal AL8t-@0'' to stop the alarm. On the other hand, since the output Q of D-FFIi is set to the AND gate (equipment),
After a predetermined period of time, when the branch output Q25 becomes ``1'', the snooze is free.

Guts Lock (9) Ne, because it will be reset again,
Alarm input terminal ALINt-@1 must be set to ``-@0'' before branch output Q26 is output. When alarm input terminal ALIN becomes 10', D-
The output Q of FF (to) is 10", and the AND
At the same time, the set pulse PU2 is outputted, and the fourth frequency dividing circuit (5) is reset again. Therefore, the frequency division output Qzs outputted after the fourth frequency division circuit (5) restarts counting is cut off by the ANDNO gate, and the output SN of the snooze 7 lip-flop (9) is "0".
Since the AND gate is blocked, the branch output Qao
is also shut off, so the alarm control loop (8) is not reset. Then, after 256 seconds, the divided output Q3
When 1 becomes @1'', the output of the NOR key becomes @0'', so Snooze Furi and Gutsulock (9) are reset, and No. 18'5Nid reaches 0''. At this time,
N.

The 4L gate uυ sets the alarm control signal ALS to 11'' and performs an alarm by snooze.

The test mote selection circuit ACB was continuously connected in 4 stages -
It consists of I'-FF-ωg-, the division output Q11 of the first frequency dividing circuit (2) is applied to the reset terminal R, and the FiN A N D gate hammer is connected to the input of the first stage T-FF-. has been done. The output ALH of the three-value detection circuit (6) and the signal of the alarm output terminal ALO are applied to the input of the NAND gate. Therefore, the test mode selection circuit counts the number 1 applied to the alarm input terminal ALIN or the old number applied to the alarm output terminal ALO, and selects each of the test mode selection circuits. Stage output T
M1. TM2, TM3, and TM4 are applied to the test pulse generation circuit αB.

The test pulse generation circuit ■ is a NAND gate @ (to) ff
It is composed of leiffi and an inverter 61□□□m111. TMl, TM2, TM for NAND Kate
3 and TM4 are applied and the content of the test mode selection circuit becomes rollJ, that is, "7" in decimal notation, a reset pulse RESBT is generated, and the reset pulse RESET is applied to the second frequency dividing circuit (3). , the sixth frequency dividing circuit (4), the set pulse generating circuit (7), the NOR gate (to), and the fourth frequency dividing circuit (
5)) On the other hand, the NAND gate is TMl
, TM4 changes the contents of the test mode selection circuit to rIX.
Specified when XOJ, NAND gate ω is TMl, T
M4 changes the contents of the test mode selection circuit to NXXIJ
is specified when , and the NAND gate area is T i142
, TM4 when the content of the test mote selection circuit 111m is "rIXOX". Therefore, depending on the count peaks and troughs of test mode selection circuit 0-, NAND gate Kasumi and NAND gate Koku, or NAND gate ω and NAND gate
6'7i may be specified at the same time. However, the signals A I, H in the NAND gate □□□
It depends on applying the signal to the alarm output terminal ALO to the NAND gate (to) the alarm output terminal ALO through the inverter. You can select either one by operating the signal. That is, the alarm input terminal ALIN
Or connect either alarm output terminal ALO to 10
By fixing it to `` and applying a pulse to the other terminal, it is possible to select the NAND or gate to which the test pulse should be output.The specific operation will be described later.

The output of NAND goo hsasm is each test pulse TE
STP1, T B 8 T P 2 s T E 8
The test pulse TESTP1 is output as T P3.
[The test pulse TB8TP2 is sent to the sixth frequency dividing circuit (4) via the NAND gate ue and the inverter
The test pulse TESTP3 is applied to the fourth frequency dividing circuit (5) via the D-Kate and inverter@, and the test pulse TESTP3 is applied to the frequency dividing circuit (3) of the stripe 2 via the NAND gate (aSi).

Therefore, by externally setting a predetermined number in the test mode selection circuit a, it is possible to select which frequency dividing circuit is to be tested.

Next, the previous version of the test mode will be explained with reference to the timing diagram of FIG. First, in order to switch from the normal operating state to the test mode, an intermediate level signal is applied to the alarm input terminal WLIN. The intermediate level of the three-value detection circuit (6) is detected, and the signal s'IN signal ALH is set to @0'' and the signal ALM is set to @1''. (Fig. 2 quadrant') 0 signal λLM is O
Since the voltage is applied to NAND'i-to through the R gate O, the NAND gate- becomes conductive, and the divided output Q+l't of the copper 1 frequency divider circuit (2) is applied to 1.
Output to alarm output terminal ALO. Therefore, in this state, measure the frequency of the alarm output terminal ALO,
The oscillation frequency of the oscillation circuit (1) can be adjusted by 8" and the 1J operation test of the first frequency dividing circuit (2) can be performed. Next, the output Q+ output to the alarm output terminal ALO
When t becomes "0'" again, the oscillation of the oscillation circuit ill is stopped by means such as separating the crystal oscillator α field from the terminal XI or IO, and the output Qu is held at @01,
Release the reset of the test mode selection circuit (to).

(Point shown in the second figure) 0 Then, @1 '' is forcibly applied to the alarm output terminal ALO from the outside to make the NAND gate □□□ conductive, and the alarm input terminal ALIN
8 pulses that become "1' are applied to the signal ALH. Therefore, the 8 pulses generated in the signal ALH are counted at the top of the test mode selection circuit via the riNANb gate ω. When the 7th pulse is counted, Test mode selection circuit output T
M4, TM3. TM2, TMl is rollJ and Nashi,
A reset signal RE8ET is output from the NAND gate via an inverter, and the second, sixth, and fourth frequency dividing circuits (3), (4), and (5) and set pulse generation circuit (7) are output.
is reset. When the 8th pulse is counted, the content of the test mode selection circuit 1e becomes [1000J, and the logical products TM1, TM4 and TM2°TM4 are 11
”, so NAND gate - and NAND gate a
becomes conductive. Therefore, the alarm input terminal AL
When a predetermined number of pulses of a predetermined frequency are applied to the alarm output terminal ALO with the signal ALH set to 0", the pulses are passed through the inverter to the NA
Applied to ND gate (to) -, but NAND gate■
is prohibited by ALH No. 100, so the pulse d
Test pulse T via N A N D gate only
It is output as E8TP1 and applied to the fifth frequency dividing circuit (4). Therefore, an arbitrary value can be set in the sixth frequency dividing circuit (4) and a test can be performed.

Next, in the above state, set the alarm output terminal ALO to °
01, and input a predetermined number to the alarm input terminal wIIN.
When pulses of both predetermined wave numbers are applied, the pulse 1 generated in the signal A L H is passed through the JNAND gate as a test pulse TESTP3, and is passed to the second frequency dividing circuit (3).
is applied to

In addition, while keeping the alarm input terminal ALIN at 0" and the I4 signal A L H all "0", the alarm output terminal AL
After setting O to ``1'', the ninth pulse is applied to the alarm input terminal ALIN. Therefore, the ninth pulse generated in the signal ALH is applied to the test mode selection circuit (TO) via the NAND gate ω, and the content of the test mode selection circuit (TO) becomes "rlool", and the logical product TM1. T
M4 and TM2. TM4 becomes @1''. That is, NA
ND gate - Go is in OJ ship state, but NAND
Since the signal ALH "[]" is applied to the gate, the test pulse TESTP3 is not output. In this state, if a predetermined number of pulses of a predetermined frequency are applied to the alarm output terminal ALO, this pulse will be applied to the inverter and NAND
It is applied as a test pulse TESTP2 to the fourth frequency dividing circuit 5) through the gates (G) and (B).

Therefore, the fourth frequency dividing circuit (5) can be tested.

Furthermore, when the 10th pulse is applied to the alarm input terminal ALIN as the alarm output terminal ALOt@1, the content of the test mode selection circuit becomes [1010J, and the k filling 711·TM4 becomes "1". , test pulse TB8TP1 can be output.

In this way, the test mode can be repeatedly selected by applying pulses to the test mode selection circuit (to) and sequentially changing the contents. Table 1 shows the contents of the test mode selection circuit and the test pulses that can be generated.

Table 1 below: If two types of test cycles are specified in the settings in the test mode selection circuit ttti, either apply a pulse from the alarm input terminal ALIN or use the alarm The selection depends on whether a pulse is applied from the output terminal ALO. Also, as shown in Table 1, the test mode selection circuit αG' does not enter the test mode until the decimal number is "6". This means that in normal operating conditions, the alarm signal or alarm output terminal AL
When the output is output to O, the alarm input terminal ALTN,
If chattering occurs in gI, AI, H, that signal may be applied to test mode selection circuit 0. However, the test mode selection circuit [phase]
11, and the chattering signal is rarely counted, but due to the delay of the alarm signal with respect to the branch output Q11,
It may be counted to some extent. In this case, the test mode is set from "7" or higher so as not to enter the test mode. By doing so, a special reset circuit for constantly resetting the test mode selection circuit (to) is not required, and the number of elements can also be reduced.

As described above, according to the present invention, the alarm input terminal and the alarm output terminal can be used as test terminals, and by providing the test mode selection circuit,
This allows internal circuits to be tested individually and quickly, and has the advantage of shortening test time and the time required for two people.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing a test mode. , ttB...Oscillation circuit, +21 +31 +41
+51...First, second, third' and fourth frequency dividing circuits, (6)...Three-value detection circuit, (7)...
...Set pulse generation circuit, (8) ...Alarm flip 70. +91...Snooze flip-flop, Bright...Test mode selection circuit, αT...Test noise generation circuit.

Claims (1)

[Claims] 1. An oscillation circuit to which a crystal oscillator or the like is connected externally to generate a reference signal, a frequency division circuit that divides the output of the oscillation circuit and outputs a pulse of a predetermined frequency, and an alarm match signal, etc. is applied. a second terminal formed by the branch output of the frequency dividing circuit and to which an alarm signal etc. is output; and an intermediate level applied to the first terminal, and a test is performed. a three-value detection circuit that outputs a signal for making an initial mode of bonito; a test mode selection circuit that sets and selects a test mode by operating signals applied to the first terminal and the second terminal; a plurality of gates specified by a plurality of outputs of a mode selection circuit, and when the output of the test mode selection circuit specifies two of the gates, the terminal is connected to either the first terminal or the second terminal. By applying a signal at a predetermined level and applying a test pulse to the other terminal, the test pulse is applied to a predetermined internal circuit via a circuit specified by the signal at the predetermined level. An integrated circuit for electronic watches.