JPS6261912B2 - - Google Patents

Description

[Detailed description of the invention]

The present application relates to a timepiece electronic circuit having an alarm function, and particularly to a timepiece electronic circuit having an alarm input terminal and an alarm output terminal. Generally, electronic circuits for watches include electronic circuits for digital display or electronic circuits for analog display using step motors, but in electronic circuits for digital display, alarm coincidence detection is performed electronically within the electronic circuit. However, in an electronic circuit for analog display, coincidence of alarms is mechanically detected and an alarm coincidence signal is applied to an alarm input terminal to cause an alarm operation. An electronic circuit for analog display using such a step motor has terminals for connecting a crystal resonator, etc.
It has a terminal for driving a step motor, a terminal to which an alarm coincidence signal is applied, an alarm output terminal, etc., and has the advantage that it can be configured with a small number of terminals. However, in order to check whether each internal circuit of a watch electronic circuit is operating correctly, a test terminal that provides a signal to put the part into a test state, and a terminal that provides a signal to operate the circuit from the outside are provided. Therefore, the advantage of having a structure with a small number of terminals was lost. Furthermore, when an alarm function or a snooze function is added, each function is tested individually, which results in a long test time. The present invention has been made in view of the above-mentioned points, and by using an alarm input terminal as a test terminal and inputting a signal from an alarm output terminal to set the state of the frequency dividing circuit, it is possible to control the internal circuit. The present invention provides an electronic circuit for a watch that does not require a terminal for testing and can be tested in a short time.
The present invention will be described in detail below with reference to the drawings. FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, in which 1 is an oscillation circuit, 2 is a first frequency divider circuit, 3 is a second frequency divider circuit, 4 is a third frequency divider circuit, 5 is a logic circuit diagram showing an embodiment of the present invention. 6 is a three-value detection circuit, 6 is a delay circuit constituting a test signal generation circuit, 7 is an extraction circuit, and 8 is a snooze storage circuit. The oscillation circuit 1 is externally connected to a crystal resonator, etc., and generates reference signals of 4, 194, and 304 Hz, and applies them to the first frequency dividing circuit 2. The first frequency dividing circuit 2 is D-FF
are connected in 16 stages, dividing the reference signal of 4, 194, and 304 Hz into 64 Hz, and the 64 Hz signal is applied to the second frequency dividing circuit 3 via NAND gates 9 and 10. The second frequency dividing circuit 3 is made up of seven stages of T-FFs connected in series, and outputs frequency divided outputs Q ₁₇ to Q ₂₃ of each stage. Divided output Q ₂₀ , Q ₂₁ , Q ₂₂ and NOR gate 11
The output T ₁ of is applied to the NAND gate 12, and the NAND
Gate 12 generates short pulses once per second depending on these inputs, and NRO gates 13, 14 and
Applied to NAND gate 15. NOR gate 1
1 and 16 constitute a flip-flop, a frequency-divided output Q ₁₇ is applied to the NOR gate 16, a frequency-divided output ₁₉ is applied to the NOR gate 11 via an inverter 17, and the other input of the NOR gate 11 is applied to A or the frequency-divided output. By connecting the frequency output Q ₁₈ to the applied B through the inverter 18, the NAND gate 1
The pulse width output from 2 can be changed. The divided output Q ₂₃ is a signal with a period of 0.5 Hz, that is, 2 seconds, and is applied to the NOR gate 14 via the NOR gate 13 and the inverter 19.
The output pulses of the NAND gate 12 are alternately outputted to the output terminals OUT1 and OUT2 by controlling the gates 3 and 14 to be made conductive alternately at one second intervals. The third frequency dividing circuit 4 is made up of seven consecutively connected T-FFs, and the output pulse of the NAND gate 12 is applied to the input via the NAND gates 15 and 20. The three-value detection circuit 5 includes inverters 21, 22, 2
3 and 24 and AND gates 25 and 26, an alarm input terminal ALIN is connected to the inverters 21 and 22, and the outputs of the AND gates 26 and 25 are sent to the cutout circuit 7 and the delay circuit 6 as signals ALH and ALM, respectively. is output to. Inverter 21, 22
have different threshold levels, and the threshold level V _T2 of the inverter 21 is set larger than the threshold level V _T1 of the inverter 22. That is, V _T1 < V _T2 < ALIN
In this case, both inverters 21 and 22 turn on and output "0", and when V _T1 < ALIN < V _T2 , inverter 22 turns on and outputs "0", but inverter 21 turns off and outputs "0". Output 1”,
In the case of ALIN<V _T1 <V _T2 , the inverter 21,
22 are both turned off and output "1". for example
Assuming that ALIN changes in the range of 0 to 1.5V, V _T2 is selected to be about 0.85V and V _T1 is selected to be about 0.65V. Table 1 shows ALIN, signals ALH, ALM, and their operations.

[Table] Also, the snooze operation changes ALH from “0” → “1” → “0” within a predetermined time after ALH becomes “0”.
This will be implemented based on the following. The cutout circuit 7 to which the signal ALH is applied includes an inverter 27, D-FFs 28 and 29, and an AND gate 30.
The signal ALH is applied to the input of the D-FF 28 via the inverter 27, and the AND gate 3
0 is the signal ALH, D-FF29 output DL2, D-
Output of FF28, i.e. 1 and 2nd frequency divider circuit 3
The output Q ₁₈ is applied to the clock terminals φ _of the D-FFs 28 and 29.
In this cutout circuit 7, the signal ALH changes from “0” to “1”.
It outputs a pulse with the same width as the pulse width of the output _Q18 from the output LE of the AND gate 30 when the signal ALH rises, and has a function of preventing chattering of the signal ALH. Snooze memory circuit 8
is a flip-flop composed of NOR gates 31 and 32, and is set by the output LE of the extraction circuit 7 and reset by the output signal _T3 of the NAND gate 33. The output SN of the snooze memory circuit 8, the output 2 of the D-FF 29 of the cutout circuit 7, and the signal ALH are applied to the NOR gate 34, and the NOR
The output signal ALS of the gate 34 cuts off the NAND gate 35 when any input is "1", makes the NAND gate 35 conductive when all inputs are "0", and outputs the output ₁₉ of the second frequency dividing circuit 3. An alarm signal generated _from Signal for setting snooze memory circuit 8
LE resets the third frequency divider circuit 4, _{and Q25} , which is output after a certain period of time, e.g. 2 to 4 seconds, is applied to the NAND gate 39, to which the signal ALH is applied. Only when ALH is “1”, output Q ₂₅ is sent from NAND gate 33 to signal T ₃
However, if ALH changes from "1" to "0" before the output _Q25 is output, the snooze memory circuit 8 is not reset and remembers that it is in the snooze state, and further After a certain period of time, for example 7 minutes, the snooze memory circuit 8 is reset by the NAND gate 40 to which the outputs Q ₂₉ , Q ₃₀ and Q ₃₁ are applied, and an alarm due to snooze is issued. On the other hand, the signal ALM is passed through the inverter 41.
Alarm output terminal applied to NAND gate 36
The output Q ₁₁ of the first frequency dividing circuit 2 is controlled to be outputted to the ALO, and the oscillation frequency of the oscillation circuit 1 can be adjusted during testing. Furthermore, the signal ALM is D-FF42,
43 and a NOR gate 44, and the clock terminal φ of the D-FFs 42 and 43
The output signal Test of the NOR gate 44 is output with a delay of at least one cycle of the output Q ₁₆ of the first frequency dividing circuit 2 applied to the NAND gates 45 and 46, and the signal Test is applied to the NAND gates 45 and 46, and is further applied to the inverters 47 and 46.
48 to the NAND gates 9 and 15,
The signals input from the alarm output terminal ALO are switched and applied to the second frequency divider circuit ₃ and the third frequency divider circuit 4, and each circuit is tested by fast forwarding. Let's do it. Further, the signal ALM is applied to the NAND gate 49, and only when the signal ALM is "1", the signal from the initial setting circuit 50 is applied to the NAND gate 49 and the inverter 51.
The reset signal Reset is outputted via the reset signal Reset to reset each circuit. Therefore, when the power is applied, the alarm input terminal ALIN will be at V _T1 <ALIN<
By configuring the circuit so that a voltage of V _T2 is applied, each circuit is reset. Figure 2 shows the normal operating state, that is, the signal ALH is "1",
This is a timing chart when ALM is “0”. The second frequency divider circuit 3 divides the 64Hz output Q ₁₆ applied via the NAND gates 9 and 10 to 32Hz
output Q ₁₇ , 16Hz output Q ₁₈ , 8Hz output Q ₁₉ , 4
Hz output Q ₂₀ , 2Hz output Q ₂₁ , 1Hz output Q ₂₂ ,
Outputs an output Q ₂₃ of 0.5Hz. When the input to the NOR gate 11 is A, the output _T1 has a pulse width shown by a solid line, and when it is B, the output T1 has a pulse width shown by a broken line. The output of the NAND gate 12 to which the outputs Q ₂₀ , Q ₂₁ , Q ₂₂ and T ₁ are applied becomes a 1 Hz signal, and the pulse width at which it becomes “0” is determined by the signal T ₁ . The NOR gates 13 and 14 to which the 0.5Hz outputs Q ₂₃ and ₂₃ are applied alternately turn on and off every second, so that the output OUT1
and OUT2 are alternately outputted with pulses that are "1" with the same pulse width as the output, and each period is 2 seconds. The slap motor is driven by connecting a step motor between the output terminals OUT1 and OUT2. In this case, inverters 52, 53
becomes the step motor driver. Next, the alarm and snooze operations will be explained using the timing chart shown in FIG. Normally, the alarm input terminal ALIN is set to "1" by a pull-up resistor, etc., the output signal ALH of the three-value detection circuit 5 is "1", and the output signal ALM is "0". The output LE of the cutout circuit 7 to which the signal ALH "1" is applied is "0", the snooze memory circuit 8 is in a reset state, the output SN is "0", and the output 2 and ALH are "1". So NOR gate 3
The output ALS of No. 4 is "0", the NAND gate 36 is cut off, and the signal _T2 is set to "0", inhibiting the output of the alarm signal. When the alarm input terminal ALIN changes from “1” to “0” at the set alarm time, the signal ALH
changes from "1" to "0", and at that time, the signal ALM momentarily becomes "1", but this is not enough to cause the delay circuit 6 to operate. When signal ALH becomes “1”, D-
The output DL1 of the FF28 becomes "1" due to the fall of the frequency-divided output _Q18 , and the output DL2 of the D-FF29 becomes "1" due to the fall of the next frequency-divided output _Q18 .
No cutting pulse is output to the output LE of the AND gate 30. Therefore, the output SN of the snooze memory circuit 8
is "0", and since the signals ALH and 2 become "0", the output ALS of the NOR gate 34 becomes "1", which makes the NAND gate 35 conductive and divides the signal _T2 into the frequency-divided output _{Q22. 19} , and further
2048 which is an audible frequency at NAND gate 37
Combines the Hz output _Q11 and outputs it to the alarm output terminal ALO. Therefore, by connecting a speaker or the like to the alarm output terminal ALO, the inverter 38 drives it to generate an alarm sound intermittently at 0.5 second intervals. In the above alarm operation state, when the alarm input terminal ALIN changes from "0" to "1" to "0" within a certain period of time (2 to 4 seconds), when the signal ALH becomes "1", the NOR gate 34 The output ALS becomes “0” and the output of the alarm sound is prohibited. On the other hand, at the falling edge of the output _Q18 , the output DL1 of the D-FF28 becomes "0", and at the next falling edge, the output DL2 of the D-FF29 becomes "0", and at this time, the AND gate 30
A pulse having the same width as the pulse of the output _Q18 is outputted to the output LE of , which sets the snooze memory circuit 8, sets its output SN to "1", and resets the third frequency dividing circuit 4. After a certain period of time (2 to 4 seconds) after this third frequency dividing circuit 4 starts frequency division again, the output Q ₂₅
Signal ALH changes from “1” to “0” before
, the signal 2 applied to the NOR gate 34 becomes "0", but the snooze memory circuit 8 remains in the set state, and since the signal ALH is "0", the output from the third frequency dividing circuit 4 is Q ₂₅ to be
Blocked by NAND gate 39, signal _T3 is unable to reset snooze memory circuit 8;
Since the output SN of the snooze memory circuit 8 remains at "1", the output ALS of the NOR gate 34 is "0", inhibiting the output of the alarm signal. This state is a snooze state, and after a certain period of time (about 7 minutes), the output is output from the third frequency dividing circuit 4.
When Q ₂₉ , Q ₃₀ , and Q ₃₁ become “1”, NAND gate 4
The output of 0 becomes "0", and the output _T3 of the NAND gate 33 becomes "1", resetting the snooze memory circuit 8. Reset snooze memory circuit 8
The output SN becomes "0" and the other inputs of the NOR gate 34, signals ALH and 2, are "0", so the output ALS becomes "1" and the alarm signal is outputted from the alarm output terminal ALO again. . On the other hand, keep the alarm input terminal ALIN at “1” for more than 4 seconds.
When it becomes "0" again, for example, when the alarm hand is turned after matching the alarm setting time and it becomes inconsistent, and it matches again after 4 seconds or more, the signals DL1 and DL2 become "0" as shown by the broken line. 0'' and a snooze memory circuit 8 for the Q ₂₅ output from the third frequency divider circuit 4 to appear on the signal T ₃ via the NAND gate 39 after 2 to 4 seconds.
is reset, the output SN becomes "0", and the snooze state is canceled. In this state, when the alarm input terminal ALIN becomes "0" again, the signal SN becomes "0", so as described above, the same operation as when the alarm input terminal ALIN is first set to "0" is performed and the alarm is output. Outputs an alarm signal from terminal ALO. Next, the operation of testing each circuit will be explained using the timing chart shown in FIG. First, in order to enter the test state, apply V _T1 < to the alarm input terminal ALIN.
Apply a voltage that satisfies ALIN<V _T2 . As a result, the output signal ALM of the three-value detection circuit 5 becomes "1", and the delay circuit 6 sets the signal Test to "1" with a delay of one cycle of the output _Q16 of the first frequency dividing circuit 2.
Further, the output T ₂ of the NAND gate 36 to which the signal is applied becomes “1”, and the output Q ₁₁ from the first frequency dividing circuit 2 is sent to the NAND gate 37 and the inverter 38.
It is output to the alarm output terminal ALD via.
This period is the first test, in which the oscillation circuit 1 is checked and the oscillation frequency is adjusted. The second test is a test of the output terminals OUT1 and OUT2, in which the oscillation of the oscillation circuit 1 is stopped by, for example, disconnecting the crystal resonator in the above state, and a relatively high frequency is applied to the alarm output terminal ALO. For example, 2KHz is applied from the outside and applied to the input T of the second frequency divider circuit 3 via the NAND gates 45 and 10 which are in a conductive state depending on the signal Test "1". Perform fast forward operation and check the output status of output terminals OUT1 and OUT2 at that time. Alternatively, if the oscillation circuit 1 continues to oscillate, the divided output Q ₁₁ of the first frequency divider circuit 2 is output to the alarm output terminal ALO, but this output Q ₁₁ is transmitted to the NAND gates 45 and 10. This output is input to the second frequency divider circuit 3 via
It is also possible to check the output status of output terminals OUT1 and OUT2 using _Q11 . The third test is an alarm and snooze test, with the oscillation stopped, the alarm input terminal ALIN is set to "0", the signal ALH is set to "0", and the ALM
is set to “0”. Since the output Q ₁₆ is not applied to the delay circuit 6, the output signal Test remains "1", but since the signal becomes "1"
NAND gate 36 allows the output of NAND gate 35 to pass through. Then the alarm output terminal
A predetermined number of pulses are externally applied to the ALO at a relatively high frequency (for example, 2KHz), and the NAND gates 45, 1
0 through the second frequency divider circuit 3 and the NAND gate 4
6, 20 to the third frequency divider circuit 4 to set the contents of the second frequency divider circuit 3 and the third frequency divider circuit 4, the signal applied to the alarm output terminal ALO is removed. and test the content output to the alarm output terminal ALO. By repeating this a predetermined number of times, the gate that generates the alarm signal can be tested. Next, the snooze test is performed after the alarm test, and the alarm input terminal ALIN is set to V _T1 < V _T2 <
ALIN, ie, "1" is applied to set the signal ALH to "1". Apply a predetermined number of pulses at a relatively high frequency (2KHz) to the alarm output terminal ALO, and
The frequency dividing circuit 3 and the third frequency dividing circuit 4 are operated in fast forward mode, but after the third frequency dividing circuit 4 is reset by the output LE and before the output _Q25 becomes "1", the alarm input terminal ALIN is set to "0" and signal ALH is set to "0". Further, the contents of the third frequency dividing circuit 4 are set to the state before the outputs Q ₂₉ , Q ₃₀ , and Q ₃₁ become “1”. In this state, the snooze memory circuit 8 is set, so the alarm output terminal
Test ALO to make sure no alarm signal is output. Furthermore, a number of pulses are applied to the alarm output terminal ALO such that the contents of the third frequency dividing circuit 4 make the outputs Q ₂₉ , Q ₃₀ , and Q ₃₁ “1”. As a result, the signal _T3 resets the snooze memory circuit 8, so it is confirmed that the snooze alarm signal is output from the alarm output terminal ALO. Next, test deactivating snooze. From the state where the above-mentioned alarm signal is being output, the signal of the alarm input terminal ALIN is set to "1", the signal ALH is set to "1", and a predetermined number of pulses are applied to the alarm output terminal ALO, and the second frequency dividing circuit 3 is activated. Then, the third frequency dividing circuit 4 is operated in fast forward mode, and after the output _Q25 becomes "1", the signal ALH is set to "0". At this time, the outputs Q ₂₉ , Q ₃₀ , and Q ₃₁ of the third frequency dividing circuit 4 are all kept in the state before they become "1". In this state, the snooze memory circuit 8 is reset by the output _Q25 and is in an alarm state, so a test is made to see if an alarm signal is output from the alarm output terminal ALO. As described above, according to the present invention, by providing a three-value detection circuit at the alarm input terminal, it becomes possible to set the alarm function, snooze function, and test function with one terminal, and furthermore, when testing, it is possible to set the alarm function, snooze function, and test function at the alarm output terminal. Tests can be performed by setting the frequency divider circuit that creates a time signal through fast forward operation by applying a pulse at a relatively high frequency from the outside, and the frequency divider circuit for measuring snooze time to any state. This has the advantage that the function of the electronic circuit for a watch can be improved without adding test terminals, etc., and the test time can be significantly shortened.

[Brief explanation of the drawing]

Fig. 1 is a logic circuit diagram showing an embodiment of the present invention, Fig. 2 is a timing chart showing the normal operation of the embodiment shown in Fig. 1, and Fig. 3 is a diagram showing the alarm operation and snooze operation of the embodiment. FIG. 4 is a timing chart showing the operation of the test function of this embodiment. Explanation of main drawing numbers, 1...Oscillation circuit, 2...1st
frequency dividing circuit, 3... second frequency dividing circuit, 4... third frequency dividing circuit
5... three-value detection circuit, 6... delay circuit, 7... cutout circuit, 8... snooze memory circuit.

Claims (1)

[Claims] 1 An oscillation circuit that generates a reference signal by connecting a crystal resonator or the like to an external terminal, a first frequency divider circuit that frequency divides the output of the oscillation circuit, and a frequency divider that divides the output of the first frequency divider circuit. an alarm input terminal to which an alarm coincidence signal is applied; and a second frequency dividing circuit that detects whether the voltage of the alarm input terminal is at a first level, a second level, or a third level. outputting an alarm signal made using a three-value detection circuit and a divided output of the first frequency dividing circuit or the second frequency dividing circuit according to the output of the three-value detecting circuit that has detected the third level; an alarm output terminal, and a third clock that measures the snooze time and generates the alarm signal to the alarm output terminal when the snooze time elapses.
a frequency dividing circuit, a test signal generation circuit which receives the output of the second level detected by the three-value detection circuit and generates a test signal; a gate for applying a signal applied from the outside to a frequency division output at an intermediate stage of the frequency circuit or an alarm output terminal to the second frequency division circuit and the third frequency division circuit; An electronic circuit for a watch characterized by fast-forwarding a frequency dividing circuit of 3.