JPS635712B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an integrated circuit for an electronic timepiece, and more particularly to an integrated circuit for an electronic timepiece that has an alarm function and is capable of testing an internal circuit using an alarm input terminal and an alarm output terminal. Generally, electronic watches using a step motor that have an alarm function mechanically detect coincidence of alarms and apply an alarm coincidence signal to an alarm input terminal to perform an alarm operation. The integrated circuit used in such analog display electronic clocks has a terminal to connect the crystal oscillator, a terminal to drive the step motor, a terminal to which the alarm matching signal is applied, and an alarm signal output to generate the alarm sound. It has the advantage of being able to be configured with a small number of terminals. However, in conventional integrated circuits, test terminals are provided for adjusting the oscillation frequency and testing internal circuits, and when adding a snooze function, a snooze terminal must be provided, which increases the number of terminals. The advantage of being able to configure the system with fewer functions is lost, and the test time also increases as the number of functions increases. The present invention has been made in view of the above-mentioned points, and by sharing a test terminal with an existing terminal and providing a circuit for specifying a test mode, it is possible to conduct a test without providing a test terminal, and also to perform a test without providing a test terminal. The present invention provides an integrated circuit for an electronic watch that can shorten the time. The present invention will be described in detail below with reference to the drawings. FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, which is an integrated circuit for an analog electronic watch with an alarm and snooze function using a step motor.
1 is an oscillation circuit; 2, 3, 4, and 5 are first, second, third, and fourth frequency dividing circuits; 6 is a three-value detection circuit; 7 is an alarm and snooze set pulse generation circuit;
8 is a flip-flop for alarm memory, 9 is a flip-flop for snooze memory, and is the first flip-flop.
1 is an alarm input terminal, ALO is an alarm output terminal that outputs an alarm signal to sound an alarm, 10 is a test mode selection circuit, and 11 is a test pulse generation circuit. The oscillation circuit 1 includes an inverter 12 and a feedback resistor.
A crystal oscillator 13 consisting of R ₁ and connected to external terminals XI and XO generates reference signals of 4, 194, and 304 Hz, and the output thereof is applied to the input of the first frequency dividing circuit 2. The first, second, and third frequency divider circuits 2, 3, and 4 have a total of 23 consecutively connected T-FFs, and the first frequency divider circuit 2, the second frequency divider circuit 3, and An inverter 14 and a NAND gate 15 are provided between the 11th stage and the 12th stage,
Further, a NAND gate 16 and an inverter 17 are also interposed between the second frequency dividing circuit 3 and the third frequency dividing circuit 4, that is, between the 16th stage and the 17th stage. The final output Q ₁₁ of the first frequency divider circuit 2 is 2048Hz, the output Q ₁₆ of the second frequency divider circuit 3 is 64Hz, and the third frequency divider circuit 4
The output Q ₂₃ is 1/2Hz. The frequency divided outputs Q ₁₈ , Q ₂₀ , Q ₂₁ , Q ₂₂ of the third frequency dividing circuit 4 are applied to the NAND gate 18, and the NAND gate 18 receives a short pulse once per second by the applied frequency divided output. A pulse is generated and a second signal is applied to the NOR gates 19 and 20 and the NAND gate 21. A frequency division output Q ₂₃ is applied to the NOR gate 19, and a frequency division output ₂₃ inverted by an inverter 22 is applied to the NOR gate ₂₀ . Since NOR gates 19 and 20 are alternately conductive every second, inverters 23 and 24 and inverter 2 are connected to output terminals OUT1 and OUT2, respectively.
A second signal SO is alternately outputted via the signals 5 and 26. A step motor is connected to the output terminals OUT1 and OUT2, and is driven by the second signal SO. Incidentally, the inverters 24 and 26 serve as drivers for the step motor. The fourth frequency dividing circuit 5, to which a second signal is applied via the NAND gate 21 and the inverter 27, is made up of nine stages of T-FFs connected in succession, and measures an alarm time and a snooze time. The three-value detection circuit 6 includes inverters 28, 29, 3
0, 31 and AND gates 32, 33, the alarm input terminal, which is the first terminal, is connected to the inverters 28, 29, and the outputs of the AND gates 32, 33 are output as signals ALM, ALH, respectively. . Inverters 28 and 29 each have different threshold levels, and inverter 2
The threshold level V _T2 of the inverter 28 is set larger than the threshold level V _T1 of the inverter 9. Normally, the alarm input terminal is set to VDD level by resistor _R2 . That is,
In the case of V _T1 <V _T2 <, the inverter 28,
29 are both turned on and their outputs are "0", so the signal ALH is "1" and the signal ALM is "0". Furthermore, when a signal of V _T1 << V _T2 is applied, the inverter 29 turns on and outputs “0”, and the inverter 28 turns off and outputs “1”, so the signal ALH is “0” and the signal ALM is “1”
becomes. Then, when a signal of <V _T1 <V _T2 is applied, both inverters 28 and 29 are turned off,
Since its output becomes "1", both signal ALH and signal ALM become "0". For example, if VDD
1.5V and the signal varies between 1.5V and 0V, then V _T1 is 0.65V and V _T2 is
It is selected to be around 0.85V. Normally, an alarm coincidence detection switch and a snooze switch are connected in series between the alarm input terminal and the ground level, and when the set alarm time arrives, the alarm coincidence detection switch closes.
The alarm input terminal is forcibly set to "0", and in order to enter the snooze state, open and close the snooze switch within a certain period of time in the alarm state, and change the alarm input terminal from "0" to "1". →Apply a “0” signal. These signals are used as changes in the output ALH of the three-value detection circuit 6 for alarm and snooze control. The set pulse generation circuit 7 detects the rising and falling edges of the signal ALH and generates the set pulse.
It outputs PU1 and PU2, and includes an inverter 34, D-FF35, 36, and NAND gate 37.
and a NOR gate 38. D-
The output _Q18 of the third frequency dividing circuit 4 is applied to the clock inputs of the FFs 35 and 36, and the falling edge of the signal ALH is applied to the NOR gate 38 which inputs the output of the D-FF 35 and the output Q of the D-FF 36. detected by
A set pulse PU2 which becomes "1" with a pulse width of one cycle of the frequency divided output _Q18 is output, and the signal
The rise of ALH is the signal ALH, D-FF35
output, D-FF36 output Q and frequency division output Q ₁₈
is detected by the NAND gate 37 which inputs
A set pulse PU1 which becomes "0" with a pulse width equal to the pulse width of the frequency-divided output _Q18 is output. The set pulse PU2 sets the alarm flip-flop 8 and also sets the NOR gate 3.
9 and the NAND gate 40, the fourth frequency divider circuit 5 is reset, and the set pulse PU1 sets the snooze flip-flop 9 to the set state. Reset. Here, the alarm operation and snooze operation will be explained. When the set alarm time arrives and the alarm input terminal becomes "0", the signal ALH becomes "1".
It falls to “0” from The alarm flip-flop 8 is set by the set pulse PU2 output at this time. On the other hand, the snooze flip-flop 9 is in the reset state, the signal SN is "0", and the output of the D-FF 36 is "0", so the NOR gate 41 outputs the alarm control signal ALS.
is set to “1”. The AND gate 42 to which the alarm control signal ALS is applied has the divided outputs Q ₂₂ and ₁₉ applied thereto, creates an intermittent alarm signal, and applies it to the NAND gate 44 via the OR gate 43 .
NAND gate 44 has a frequency divided output of 2048Hz
_Q11 is applied, superimposed on the alarm intermittent signal, and sent to the alarm output terminal via the inverter 45.
Output to ALO. On the other hand, the reset fourth frequency dividing circuit 5 resumes counting the second signal, and after a certain period of time, 128 seconds, outputs
Q ₃₀ becomes “1”. At this time, since the output of the flip-flop 9 in the reset state is "1", the output _Q30 resets the alarm flip-flop 8 via the AND gate 46. Therefore, the NOR gate 41 is cut off by the output of the alarm flip-flop 8, and the alarm control signal
ALS becomes “0” and the alarm stops. Snooze applies a signal from "0" to "1" to "0" to the alarm input terminal within a predetermined time in an alarm state. Alarm input terminal
When ALIN changes from “0” to “1”, the signal ALH rises from “0” to “1”, and at this time, NAND
A set pulse PU1 is output from the gate 37,
The snooze flip-flop 9 is set and the fourth frequency divider circuit 5 is reset. Since the snooze flip-flop 9 is set, the signal SN becomes "1", and the output of the D-FF 36 is also "1", so the NOR gate 41 sets the alarm control signal ALS to "0" and causes an alarm. to stop. On the other hand, the output of D-FF36 is
Since the AND gate 47 is in a conductive state, when the frequency division output Q ₂₅ becomes " ₁ " after a predetermined time, the snooze flip-flop 9 is reset again. To,
The alarm input terminal must be changed from "1" to "0". When the alarm input terminal becomes "0", the output of the D-FF 36 becomes "0", shutting off the AND gate 47, outputting the set pulse PU2, and resetting the fourth frequency dividing circuit 5. Therefore, the fourth frequency dividing circuit 5
The divided output Q ₂₅ output after restarts counting is
It is blocked by the AND gate 47, and the output of the snooze flip-flop 9 is "0", and the AND
Since the gate 46 is blocked, the divided output Q ₃₀
Since the alarm flip-flop 8 is also cut off, the alarm flip-flop 8 is not reset. Then, after 256 seconds, the divided output
When Q ₃₁ becomes "1", the output of NOR gate 48 becomes "0", so snooze flip-flop 9
is reset, and the signal SN becomes "0". At this time, the NOR gate 41 outputs the alarm control signal ALS
is set to "1" and an alarm is generated by snooze. The test mode selection circuit 10 consists of T-FFs 49, 50, 51, and 52 connected in four stages, and a NAND gate 53 is connected to the input of the first-stage T-FF 49. The output ALH of the three-value detection circuit 6 and the signal of the alarm output terminal ALO are applied to the input of the NAND gate 53. Therefore, the test mode selection circuit 10 has an alarm input terminal
By fixing either ALIN or the alarm output terminal ALO to "1" and applying a predetermined number of pulses to the other, the pulses are counted. The contents set in the test mode selection circuit 10 are the outputs TM1, TM2, TM of each stage.
3. Test pulse generation circuit 11 by TM4
is applied to However, in the normal operating state, when the alarm signal is output from the alarm output terminal ALO, the alarm input terminal is set to "1" when entering snooze. The output of
Until the alarm control signal ALS of the NOR gate 41 is set to "0", the signal of the alarm output terminal ALO and the signal
A logical AND with ALH (this signal includes chattering) is output at NAND gate 53. Therefore, this signal is sent to test mode selection circuit 1.
You must make sure that 0 is not counted. Therefore, T-FF49 of the test mode selection circuit 10,
The frequency divided output Q11 of the first frequency dividing circuit 2 used for creating an alarm sound is applied to each reset terminal R of 50, 51, and ₅₂ . Therefore, when a pulse is generated at the output of the NAND gate 53, it is always reset by the divided output _Q11 . Therefore, a reset circuit for constantly resetting the test mode selection circuit 10 in the normal operating state can be omitted. Furthermore, as will become clear in the explanation below, the time delay between the divided output Q ₁₁ and the alarm signal may cause erroneous counting.
Test mode selection circuit 1 when entering test mode
The count content of 0 is set to "7" or more. The test pulse generation circuit 11 is a NAND gate 5
4, 55, 56, 57 and inverters 58, 5
Consists of 9, 60, 61, NAND gate 5
4 generates a reset pulse RESET when the content of the test mode selection circuit 10 becomes "7" in decimal notation, and the second frequency divider circuit 3, the third frequency divider circuit 4,
set pulse generation circuit 7 and NOR gate 39,
The fourth frequency divider circuit 5 is reset via the NAND gate 40. The NAND gate 55 includes TM4,
TM1, NAND gate 56 has TM4, TM1
However, TM4, 2 and ALH are applied to the NAND gate 57, and each NAND gate 55, 56, 57 has an alarm output terminal.
A signal applied to ALO is commonly applied via an inverter 62. Then, each output is a test pulse TESTP1, TESTP2,
Output as TESTP3, test pulse
TESTP1 is NAND gate 16 and inverter 1
7 to the third frequency divider circuit 4, the test pulse
TESTP2 is NAND gate 21 and inverter 2
7 to the fourth frequency divider circuit 5, the test pulse
TESTP3 is applied to the second frequency divider circuit 3 via the NAND gate 15. Therefore, when "7" or more is set, the test mode selection circuit 10 determines which frequency dividing circuit to select depending on the content of the count. Next, the operation in the test mode will be explained with reference to the timing diagram of FIG. First, in order to change from normal operating state to test mode, connect the alarm input terminal.
Apply an intermediate level signal to ALIN. The three-value detection circuit 6 detects the intermediate level and sets the signal ALH to “0”.
Then, set the signal ALM to “1”. (Point a in Figure 3).
Since the signal ALM is applied to the NAND gate 44 via the OR gate 43, the NAND gate 44
becomes conductive, and the divided output of the first frequency dividing circuit 2
Connect _Q11 to alarm output terminal via inverter 45
Output to ALO. Therefore, in this state,
The frequency of the alarm output terminal ALO can be measured, the oscillation frequency of the oscillation circuit 1 can be adjusted, and the operation of the first frequency dividing circuit 2 can be tested. Next, output Q ₁₁ is output to alarm output terminal ALO.
When becomes "0", the oscillation of the oscillation circuit 1 is stopped by means such as isolating the crystal resonator 13 from the terminal XI or IO, the output _Q11 is held at "0", and the test mode is started. The selection circuit 10 is released from reset. (Point b in Figure 3). Then, "1" is forcibly applied to the alarm output terminal ALO from the outside to make the NAND gate 53 conductive, and a pulse that becomes "1" is applied to the alarm input terminal 8.
Apply . Therefore, the eight pulses generated in the signal ALH are counted by the test mode selection circuit 10 via the NAND gate 53. When the seventh pulse is counted, the output of the test mode selection circuit 10
TM4, TM3, TM2, and TM1 become "0111", and the reset signal RESET is output from the NAND gate 54 via the inverter 58, and the second,
The third and fourth frequency dividing circuits 3, 4, 5 and the set pulse generating circuit 7 are reset. Also, when the eighth pulse is counted, the test mode selection circuit 10
The content of is "1000" and the logical products 1.TM4 and 2.TM4 become "1", so that the NAND gate 55 and the NAND gate 57 become conductive. Therefore, set the alarm input terminal to “0”,
That is, when a predetermined number of pulses of a predetermined frequency are applied to the alarm output terminal ALO while the signal ALH is set to "0", the pulses are applied to the NAND gates 55 and 57 via the inverter 62.
Since the NAND gate 57 is inhibited by the signal ALH, the pulse is outputted as a test pulse TESTP1 only through the NAND gate 55 and applied to the third frequency dividing circuit 4. Therefore, an arbitrary value can be set in the third frequency dividing circuit 4, and a test can be performed. Next, in the above state, the alarm output terminal
While ALO is set to “0”, connect the alarm input terminal to the alarm input terminal.
When a predetermined number of pulses of a predetermined frequency are applied to ALIN, the pulses generated in the signal ALH are generated by the NAND gate 5.
7, it is output as a test pulse TESTP3 and applied to the second frequency dividing circuit 3. In addition, after setting the alarm output terminal ALO to "1" while keeping the alarm input terminal "0", that is, the signal ALH "0", the alarm input terminal
Apply the 9th pulse to ALIN. Therefore, the ninth pulse generated in the signal ALH is applied to the test mode selection circuit 10 via the NAND gate 53, and the content of the test mode selection circuit 10 is "1001".
Therefore, the logical products TM1・TM4 and 2・TM4 become “1”. That is, the NAND gates 56 and 57 become conductive, but since the signal ALH "0" is applied to the NAND gate 57, the test pulse
TESTP3 is not output. When a predetermined number of pulses of a predetermined frequency are applied to the alarm output terminal ALO in this state, the pulses are applied to the inverter 62 and
Test pulse via NAND gate 56
It is applied to the fourth frequency dividing circuit 5 as TESTP2. Therefore, the fourth frequency dividing circuit 5 can be tested. Furthermore, with the alarm output terminal ALO set to “1”,
When the 10th pulse is applied to the alarm input terminal, the content of the test mode selection circuit 10 becomes "1010" and the logical product 1·TM4 becomes "1", making it possible to output the test pulse TESTP1. In this manner, the test mode can be repeatedly selected by applying pulses to the test mode selection circuit 10 and sequentially changing the contents. Table 1 shows the contents of the test mode selection circuit 10 and test pulses that can be generated.

[Table] When two types of test pulses are specified in the settings in the test mode selection circuit 10, the pulses are applied from the alarm input terminal or from the alarm output terminal ALO, as described above. The choice can be made depending on whether the pulse is applied. In addition, as shown in Table 1, the test mode selection circuit 1
0 is a decimal number that is set to not enter test mode until it reaches "6". As mentioned above, this is done so that the test mode selection circuit 10 may be erroneously counted due to the time delay between the reset frequency divided output Q ₁₁ and the alarm signal in the normal operating state. This gives them some leeway. As described above, according to the present invention, since the alarm input terminal and the alarm output terminal can be used as test terminals, an increase in the number of terminals can be prevented, and the reset of the test mode selection circuit can be
Since this is done using a divided output with the same frequency as the alarm signal, no special reset circuit is required.
The number of elements is reduced. Furthermore, internal circuits can be tested individually using the test mode selection circuit.
This greatly reduces test time.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing diagrams showing the operation of the embodiment shown in FIG. 1... Oscillation circuit, 2, 3, 4, 5... 1st, 2nd, 3rd and 4th frequency dividing circuit, 6... Three-value detection circuit, 7... Set pulse generation circuit, 8... Alarm Flip-flop, 9... Snooze flip-flop, 10... Test mode selection circuit, 11...
...Test pulse generation circuit.

Claims (1)

[Claims] 1. Formed using a frequency dividing circuit that divides the frequency of a reference signal and outputs a pulse of a predetermined frequency, a first terminal to which an alarm match signal, etc. is applied, and a plurality of frequency dividing stage outputs of the frequency dividing circuit. a second output terminal to which an alarm signal is output; and three-value detection for detecting whether the voltage at the first terminal is at a first level, a second level, or a third level. a gate circuit that outputs an arbitrary frequency dividing stage output of the frequency dividing circuit to the second terminal using a detection output when the three-value detection circuit detects a second level; a test mode selection circuit that counts pulses generated at the detection output when the three-value detection circuit detects a first level based on a signal forcibly applied from the test mode selection circuit; and a test pulse generation circuit that outputs a test pulse that detects the internal circuit and puts the internal circuit in a test mode, and in a normal operating state, a predetermined number of signals output from the second terminal are sent to the test mode selection circuit. An integrated circuit for an electronic timepiece, characterized in that an output of an arbitrary frequency dividing stage of the frequency dividing circuit is applied to a reset terminal of the test mode selection circuit in order to prevent counting.