JPS6150266B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog electronic timepiece that includes an oscillation detection circuit and controls the output of drive pulses for a pulse motor.

In conventional analog electronic clocks, if the oscillator including the crystal oscillator fails or the oscillator or frequency divider circuit stops operating due to a drop in battery voltage due to temperature change, the pulse motor drive pulses continue to be output. This caused current to continue flowing through the pulse motor coil, significantly shortening battery life.

The purpose of the present invention is to improve the above-mentioned drawbacks, detect oscillation with an oscillation detection circuit, and prevent the output of drive pulses for the pulse motor when the oscillation is stopped, thereby eliminating the current flowing through the coil of the pulse motor and extending battery life. Our goal is to provide an analog electronic watch that will never fail.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit block diagram of the analog electronic timepiece of the present invention, and FIG. 2 is a diagram of main voltage waveforms in FIG. 1.

1 is an oscillator that uses a crystal oscillator as a time reference. 2 is a frequency dividing circuit which receives the oscillation signal from the oscillator 1 and outputs a frequency divided signal of 1 Hz and _P5 . 3 is a waveform shaping circuit, and the frequency dividing circuit 2
It inputs a 1Hz signal from , performs waveform shaping, and outputs a waveform-shaped signal _P1 . 7 is an oscillation detection circuit;
Transmission gate 7a, capacitor 7
b, and a resistor 7c, and the oscillation output signal from the oscillation circuit 1 or the divided signal _P5 from the frequency dividing circuit 2 as shown in this embodiment is connected to the control terminal (φ) of the transmission gate 7a. It is input to input terminal A and performs a switch operation. or,
Output terminal B is a capacitor 7b connected in parallel.
It is connected to the ground (V _SS potential) via a resistor 7c, performs a charging/discharging operation with the frequency-divided signal _P5 as input, and outputs a detection signal _P6 . Reference numeral 4 denotes a drive circuit, which is composed of an AND gate 4a, a binary flip-flop 4b (hereinafter referred to as FF), NAND gates 4c and 4d, and inverters 4e and 4. One input terminal of the AND gate 4a is supplied with the output _P1 of the waveform shaping circuit 3, the other input terminal is supplied with the output _P6 of the oscillation detection circuit 7, and the output of the AND gate 4a is supplied with the output P1 of the waveform shaping circuit 3. The terminal is connected to the input terminal of the binary FF 4b, and also to one input terminal of each of the NAND gates 4c and 4d, and outputs an output signal _P2 . binary
The output terminal Q of FF4b is connected to the other input terminal of the NAND gate 4c, and the inverted output terminal is connected to the NAND gate 4c.
It is connected to the other input terminal of gate 4d.
The output terminal of the NAND gate 4c is the inverter 4
A pulse motor driving pulse _P3 is output to the driving pulse output terminal C via e. NAND gate 4d
The output terminal outputs a pulse motor drive pulse _P4 to the drive pulse output terminal D via the inverter 45.

5 is a pulse motor drive coil. 6 is a pulse motor, and drive pulses P ₃ , P ₄ for the pulse motor are alternately outputted from the drive circuit 4.
It is rotated in steps.

Next, the operation of the analog electronic timepiece with the above configuration will be explained.

In the normal state, the oscillator 1 is oscillating, and the oscillation signal from the oscillator 1 causes the frequency dividing circuit 2 to output a frequency divided signal of 1 Hz and a frequency divided signal _P5 as shown in FIG. Since the frequency-divided signal _P5 is output, the oscillation detection circuit 7 turns on the transmission gate 7a when the frequency-divided signal _P5 is at "H" level, and outputs the frequency-divided signal _P5. is passed from input terminal A to output terminal B of the transmission gate 7a. At this time, when the "H" level signal of the frequency-divided signal _P5 is output from the output terminal B of the transmission gate 7a, the capacitor 7
b is charged, and the detection signal _P6 becomes an "H" level signal. Furthermore, when the frequency divided signal _P5 reaches the "L" level, the transmission gate 7a is turned OFF.
The electric charge charged in the capacitor 7b starts to be discharged through the resistor 7c, but the capacitor 7b is charged again as the next divided signal _P5 reaches the "H" level and is detected as shown in Fig. 2. The signal _P6 maintains an "H" level signal while the frequency-divided signal _P5 is output.

When the detection signal _P6 is at the "H" level, the AND gate 4a of the drive circuit 4 is open, and the frequency-divided signal 1Hz is shaped by the waveform shaping circuit 3 to produce a waveform-shaped signal as shown in FIG. 2A. The signal P ₁ is input as a signal P ₂ as shown in FIG. 2B to the input terminal of the binary FF 4b and to the NAND gates 4c and 4d.

The signal P ₂ is alternately output from the outputs of the NAND gates 4c and 4d every second, and is passed through the inverters 4e and 4 to the drive pulse output terminals C,
At D, drive pulses P ₃ and P ₄ for the pulse motor are output as shown in FIG. 2 C and D. A current i is applied to the coil 5 by the pulse motor drive pulses P ₃ and P ₄ .
is caused to flow, and the pulse motor 6 starts rotating in steps. In conventional analog electronic watches, there is no oscillation detection circuit 7 and AND gate 4a,
As shown by the dotted line, the waveform shaping signal P ₁ is directly supplied to the binary FF 4b and the NAND gates 4c and 4d, so during normal operation as described above, for example, the pulse motor drive pulse P ₃ is output. During the period _t3 during which the current i is flowing through the coil 5, the battery voltage drops due to a failure of the crystal oscillator or temperature, and the waveform shaping signal _P1 becomes "H".
If the oscillation stops in the state of the current level, the current i will continue to flow through the coil 5 as shown by the dotted line in FIG. Since the oscillator 1 stops oscillating due to the provision of the oscillation detection circuit 7, the frequency division signal _P5 from the frequency division circuit 2 is also stopped, and the output of the oscillation detection circuit 7 is also changed to t in FIG. It becomes "L" level as shown from ₅ to _t6 . That is, when the frequency-divided signal _P5 is no longer output, the transmission gate 7a of the oscillation detection circuit 7 is activated.
The state becomes OFF, and the electric charge charged in the capacitor 7b is discharged through the resistor 7C, and the voltage shown in Fig. 2 is reached.
As shown from _t5 to _t6 , the detection signal _P6 becomes "L" level. When the detection signal P ₆ becomes "L" level, the AND gate 4a of the drive circuit 4 is closed and a "L" level signal is forcibly output from the output terminal, so that the NAND gates 4c and 4d are Each becomes "H" level.

Therefore, the same level signals P ₃ and P ₄ of "L" are output to the drive pulse output terminals C and D at the same potential during the period t ₅ to _{t 6} shown in FIG. Current i never flows through 5.

In this embodiment, the detection signal _P6 from the oscillation detection circuit 7 is connected to the AND gate 4a of the drive circuit 4, but in another embodiment, the AND gate 4a of the drive circuit 4 is connected as shown by the dotted line in FIG. For short, the waveform shaping signal _P1 from the waveform shaping circuit 3 is directly converted to binary.
Input terminal of FF4b and NAND gate 4c,
The same effects as in the first embodiment can be obtained by connecting the detection signal _P6 to the input of the NAND gate 4d and inputting the detection signal P6 to the NAND gates 4c and 4d as three-input NAND gates.

Furthermore, the oscillation detection circuit 7 in FIG. 1 can be replaced with a modified oscillation detection circuit 8 as shown in the circuit block diagram of _FIG. A pulsing circuit 8 as an input, an inverter 8a receiving a signal from the pulsing circuit 8 as an input, and the inverter 8a.
A transmission gate 8b is connected to the input terminal A with the signal from the output terminal of the input terminal A, and the frequency-divided signal _P5 is connected to the control terminal;
A capacitor 8c and a resistor 8d, one terminal of which is connected to the output terminal B of the transmission gate 8b and the other terminal connected to _VDD , and an output terminal B of the transmission gate 8b and the capacitor 8.
c, and an inverter 8e that is connected to a terminal connected to a resistor 8d and outputs a detection signal _P6 . Normally, when the oscillator 1 is oscillating, the frequency is divided from the frequency dividing circuit 2. When the signal _P5 is being output and the output signal from the pulsing circuit ₈ , which outputs a pulse in synchronization with the rise of the frequency-divided signal P5, is at the "L" level, the transmission gate 8b is in the "L" level state. The capacitor 8c becomes OFF and begins to be charged via the resistor 8d. However, when the signal from the pulse generator 8 becomes an "H" level signal, the transmission gate 8b becomes ON and the inverter 8a is turned OFF. Since the output of the inverter 8c is at the "L" level, the electric charge charged in the capacitor 8c is discharged, and the detection signal _P6 at the "H" level is outputted to the output terminal of the inverter 8e.

While the frequency dividing signal _P5 continues to be output from the frequency dividing circuit 2 in this manner, an output signal is also being output from the pulse generator 8, and the capacitor 8c
The amount of electric charge charged is small, the charging voltage signal E always maintains the "L" level, and the detection signal _P6 maintains the "H" level.

Furthermore, when the oscillation stops, the frequency-divided signal _P5 is no longer output, and the output signal from the pulse generator 8 also goes to "L" level, turning the transmission gate 8b into an OFF state.

When the transmission gate 8b is turned off, the capacitor 8c is charged via the resistor 8d, and the charging voltage signal E is set to "H" level, so the detection signal _P6 is set to "L" by the inverter 8e.
level and the drive pulses for the pulse motor are set to the same potential as the "L" level, and a current i is applied to the coil 5.
I try not to let it flow.

As described above, in the present invention, by equipping a conventional analog electronic watch with an oscillation detection circuit, the crystal oscillator can stop oscillating due to a drop in battery voltage due to temperature, or if the user drops the watch while carrying it. If the oscillation stops due to damage, the pulse motor drive pulses will continue to be output.
This has been extremely effective in providing an analog electronic timepiece with a long battery life in which unnecessary losses are reduced by preventing current from continuing to flow through the coil and significantly impairing the battery life.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an analog electronic timepiece according to the present invention, FIG. 2 is a main voltage waveform diagram in FIG. 1, and FIG. 3 is a circuit block diagram of another embodiment of the oscillation detection circuit. 1... Oscillator, 2... Frequency dividing circuit, 3... Waveform shaping circuit, 4... Drive circuit, 4a... AND gate, 4c, 4d... NAND gate, 5... Coil, 6... Pulse motor, 7...Oscillation detection circuit, _P1 ...Waveform shaping signal, _P3 , _P4 ...Drive pulse for pulse motor, P5...Divide circuit, _{P6 ...} Detection signal, 8...Oscillation detection circuit.

Claims (1)

[Claims] 1. An oscillator that uses a crystal as a time reference, a frequency dividing circuit that receives the oscillation signal of the oscillator as input, a waveform shaping circuit that receives an arbitrary divided signal from the frequency dividing circuit as input and performs waveform shaping, and the waveform shaping circuit. To detect when the oscillator has stopped oscillating in an analog electronic clock consisting of a pulse motor and a drive circuit that receives signals from the circuit and outputs pulse motor drive pulses to the output terminal. An oscillation detection circuit which inputs a signal from the oscillation circuit or the frequency dividing circuit is provided, and the drive circuit is provided with a gate means for making the potential of each pulse motor output terminal the same potential, An analog electronic timepiece characterized in that the detection signal controls the gate means of the drive circuit so that the potentials of the output terminals for each pulse motor are the same potential.