JPS62285090A - Integrated circuit with testing function - Google Patents

Abstract

PURPOSE:To achieve a reduction in the cost, by supplying a clock pulse to a functioning circuit from a test terminal once prohibiting an input thereto from a preceding frequency dividing stage. CONSTITUTION:A frequency dividing stage 3 and a driving circuit 4 composes a functioning circuit to be tested. Normally, with a test terminal 6 held at '0', a frequency dividing stage 2 starts, an output thereof is inverted in the level through a gate circuit 5 and supplied to a frequency dividing stage 3 to generate a pulse for driving a motor from a circuit 4 receiving the output from the frequency dividing stage 3. When carrying out a test, a testing clock pulse is supplied to the terminal 6 with the pulse width at the '0' level being smaller than a half that of the output from the preceding frequency dividing stage 2. The frequency dividing stage 2 is reset by '1' level of the clock pulse. On the other hand, the clock pulse is inverted in the level with the circuit 5 and fed to the frequency dividing stage 3 to perform a frequency dividing operation and an output pulse is generated from the circuit 4 according to the output pulse thereof. Thus, the frequency dividing stage 3 and the circuit 4 are tested.

Description

[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to an integrated circuit with a test function.

[Prior Art] For example, integrated circuits for quartz watches require high precision and reliability. Therefore, during manufacturing, it is necessary to test each integrated circuit to determine whether the frequency dividing circuit operates normally, and the time required for this test becomes a major problem.

Conventionally, in order to perform this test, a test terminal is provided on the integrated circuit, and a high-speed external clock pulse for testing is supplied from this terminal to an intermediate stage of the frequency dividing circuit. During this test, it is necessary to stop the previous frequency dividing stage, so in addition to the test terminals described above, a stop terminal was also provided.

[Problems to be Solved by the Invention] Conventional devices require test and stop terminals, which increases the chip size of the integrated circuit, leading to an increase in cost.

The present invention provides a functional integrated circuit that can be tested using only one test terminal.

[Means for solving EljlI 11 points] The present invention supplies a test clock pulse to a test terminal from the outside, inputs this clock pulse to a functional circuit, and at the same time inputs the clock pulse to a functional circuit, and at the same time inputs the clock pulse to a functional circuit by supplying a test clock pulse to a test terminal from the outside. It is designed to prohibit supply to functional circuits.

[Example] In FIG. 1, 1 is an oscillator that generates a reference frequency signal, 2 and 3 are frequency dividing stages, 4 is a motor drive circuit, and frequency dividing stage 3
The drive circuit 4 constitutes a functional circuit to be tested. 5 is a gate circuit, and 6 is a test terminal.

In the above configuration, normally the test terminal 6 is
It is held at “0” as in . Therefore, the frequency dividing stage 2 operates, and its output is level-inverted and supplied to the frequency dividing stage 3 via the gate circuit 5 as shown in FIG. 2C. In response to the output from the frequency dividing stage 3, a drive pulse for the motor is generated from the drive circuit 4, and the motor is driven.

When performing a test, a test clock pulse having a "0" level pulse width shorter than the pulse width of 172 from the frequency dividing stage 2 is externally supplied to the test terminal 6 as shown in FIG. The frequency dividing stage 2 is reset by the "1" level of this clock pulse, and no pulse is generated from its output, and supply to the frequency dividing stage 3 is prohibited.

On the other hand, the clock pulse is converted into a second clock pulse by the gate circuit 5.
As shown in FIG. C, the signal is level-inverted and supplied to the frequency dividing stage 3, and the frequency dividing stage 3 performs a frequency dividing operation. Drive circuit 4 by its output
An output pulse is generated from , and the frequency dividing stage 3 and the drive circuit 4 are tested by this output pulse.

Next, other embodiments will be described. In Figure 3,
7.8 is a frequency division stage, the frequency division stage 7 is used for driving a motor, for example, and the frequency division stage 8 is connected to the input of, for example, a snooze counter (not shown).

In this case, the frequency dividing stage 8 and the snooze counter constitute a functional circuit. 9 is a flip-flop circuit,
10.11 is a gate circuit, and the same number as in FIG. 1 indicates the same thing.

In the above configuration, the test terminal 6 is normally held at "0". Therefore, the output Q of the flip-flop circuit 9 is held at "1", the gate circuit 10 is opened, and the output from the frequency dividing stage 2 is passed through the gate circuit 10.11 as shown in FIG.
The signal is supplied to the frequency dividing stage 8 as follows.

When performing a test, the same clock pulse as in the previous embodiment is supplied to the test terminal 6.

As a result, the flip-flop circuit 9 is reset, the gate circuit 10 is closed, and the input from the frequency dividing stage 2 to the frequency dividing stage 8 is prohibited.

On the other hand, the clock pulse is supplied to the division stage 8 via the gate circuit 11, and the frequency division stage 8 and the snooze counter are tested.

In each of the above embodiments, a case has been described in which a frequency dividing stage, a motor drive circuit, and a counter are used as functional circuits. It can be applied to anything.

[Effects of the Invention] According to the present invention, by supplying a clock pulse from a test terminal, the input to the functional circuit from the frequency dividing stage in the preceding stage is suppressed, and the clock pulse is supplied to the functional circuit. Therefore, a functional circuit can be tested using only one test terminal, and the chip size of the integrated circuit can be reduced, which is extremely effective in reducing costs.

In particular, when testing a frequency division stage, the clock pulse is supplied from the middle of the frequency division stage, so the testing time can be shortened, which is highly effective when testing a large number of integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram showing one embodiment of the present invention, FIG. 2 is a time chart for explaining the operation, and FIG. 3 is a logic circuit diagram showing another embodiment. 1... Oscillator 2.3... Frequency division stage 4... Drive circuit 5... Gate circuit 6... Test terminal 8... Frequency division stage 9... Flip-flop circuit 10.11.・Gate circuit

Claims (1)

[Claims] a frequency dividing circuit that divides a reference frequency signal; a functional circuit that operates according to an output from a desired frequency dividing stage of the frequency dividing circuit;
A test terminal is provided that prohibits the supply of the output from the desired frequency dividing stage to the functional circuit by supplying the test clock pulse, and also supplies the test clock pulse to the functional circuit. Integrated circuit with test function.