GB2222689A - Testing logic circuits - Google Patents

Abstract

An input circuit for executing a test mode of a logic circuit such as a ripple counter comprises an input/test pad (40) serving both as an input terminal and test input terminal, a first transistor (107) for controlling the voltage of a node (106) according to signal levels of inputs from the pad (40), a second transistor (103) for controlling the voltage of said node (106), transmission gates (102, 105) for controlling nodes respectively according to input signal levels from the pad (40), a first inverter (150) for inverting the voltage at said node (106) and applying it to a second inverter (151) and a first logic gate (27) to control the same, the second inverter (151) applying its output to a second logic gate (18) to control the same. In the normal mode, clock pulses (1) traverse eight toggle flip flops (6-16, 29, 31) and two gates (18, 20) but in a test mode traverse two flip flops (29, 31) and two gates (27, 20). <IMAGE>

Description

INPUT CIRCUIT FOR EXECUTING TEST MODE FUNCTION The present invention relates to an input circuit for executing a test mode function of a logic circuit.

More particularly, for example, it relates to an input circuit for use in testing a logic circuit in the form of an integrated circuit (IC).

Conventionally, an IC such as an octal ripple counter or the like is provided with an external pin specially for use in testing of the IC, i.e. for executing a test mode function. However, there is a general need to reduce the pin count and package size of ICs as far as possible. Consequently, the provision of a special test pin is undesirable.

According to the present invention, there is provided an input circuit for executing a test mode, comprising an input/test pad common for an input terminal and test input terminal, a first transistor for controlling the voltage of a node according to signal levels of inputs from the pad, a second transistor for controlling the voltage of said node, transmission gates for controlling nodes respectively according to input signal levels from the pad, a first inverter for inverting the voltage at said node and applying it to a second inverter and a first logic gate to control the logic gate, the second inverter inverting the output of the first inverter and applying it to the input terminal of a second logic gate to control the same, whereby the number of separate exterior pins required for test modes may be reduced.

Thus, the invention can provide an input circuit for executing a test mode function without a special pin. In particular, the invention eliminates the necessity of a separate test pin that has been previously required to exclusively execute the test mode function and enables testing to be carried out using any of the input pins. The invention thus not only enhances the construction of the IC for better efficiency but also has the effect of reducing the cost of the whole assembly.

Reference will now be made, by way of example, to the accompanying drawings in which: Fig. 1 shows a previously-proposed input circuit for executing a test mode function; Fig. 2 shows an input circuit for executing a test mode function, embodying the present invention; Fig. 3 shows an octal ripple counter incorporating the input circuit of Fig. 2; Fig. 4 illustrates the timing of signals in the circuits of Fig. 1 and Fig. 3; and Fig. 5 shows a simulation output display of an operational state of the circuit of Fig. 3.

The reference numerals in the drawings indicate the following: numeral 1 indicates a clock input terminal; 2,23,25,34,36 indicate respective inverters; 4,18,20,27 respective NAND GATES; 22 a test input terminal; 6,8,10,12,14,i6,29,31 toggle flip-flops; 102 and 105 transmission gates; and 103 and 107-111 transistors.

Fig. 1 shows a previously-proposed circuit construction for testing an octal ripple counter comprising eight toggle flip flops 6,8,10,12,14,16,29 and 31, in which clock pulses input through input terminal 1 are applied via inverter 2 to one of the input terminals of NAND GATE 4 and also via inverter 25 to one of the inputs of NAND GATE 27. Test input terminal 22 is connected to an exterior test pin and to the other input terminal of NAND GATE 27, and is also connected via inverter 23 to the respective inputs of NAND GATES 4 and 18.

The output of NAND GATE 4 is supplied to the clock terminal CK of the first toggle flip flop 6, whose inverted output Q1 is connected to the clock terminal of the second toggle flip flop 8. The latter in turn is connected from its inverted output Q2 to the clock terminal CK of the next toggle flip flop, and so on in succession, up to the inverted output Q5 of the fifth toggle flip flop 14 which is connected to the clock terminal CK of the sixth toggle flip flop 16. The inverted output Q6 of the sixth flip flop is connected to the other input of NAND GATE 18. The outputs of NAND GATES 18 and 27 are applied to the respective inputs of NAND GATE 20, whose output is connected to the clock terminal of the seventh toggle flip flop 29.

The latter's inverted output Q7, which is connected to the clock terminal of the eighth toggle flip flop 31, together with the inversion output Q8 of the flip flop 31, is used for respective chip tests.

Further, output 37 receives input from input 33 via inverters 34 and 36 such that an extra external pin is required.

The operation of this circuit will now be described. As shown in Fig. 4(1) and (2), the application of clock 1 having a 1 us cycle period and the "low" state of test input terminal 22 connected to the exterior test pin cause the output of inverter 23, that is one input terminal of NAND GATE 4, to be in a "high" state. This allows the clock pulse to be applied via inverter 2 and NAND GATE 4 to the first toggle flip flop 6, whose output Q1 rises at the falling edge of the clock pulse and falls at the next falling edge so as to produce a pulse waveform having a 2 us cycle period.

In the same manner, every successive toggle flip flop makes another pulse division by two so that output terminals Q7B and Q8B respectively have waveforms with 128 11s and 256 ,us cycle periods.

However, when test input 22 is "high" in the test mode, the output from inverter 23 goes "low" to interrupt the clock input to NAND GATE 4 and also the input to NAND GATE 18.

Meanwhile, a "high" signal is applied to NAND GATE 27 so that it receives the clock input coming via inverters 2 and 25, its output being applied via NAND GATE 20 to the clock terminal CK of the seventh toggle flip-flop 29. Consequently, in a test mode, the exterior clock input 1 is directly applied to the clock terminal CK of toggle flip-flop 29 such that the T-flip-flop 29 and T-flip flop 31 respectively operate like the first and second T-flip flops 6 and 8.

In this way, the testing time with a test mode is reduced to 1/64th of the time required for testing with a normal operation mode. However, this type of circuit requires an exterior pin for exclusive use with a test mode to execute its test mode function, thus resulting in a disadvantageous increase of the number of pins and consequent cost increase for manufacturing chip assemblies and keyboards.

The present invention can provide a circuit for removing such a disadvantage, and one embodiment will now be described with reference to Fig. 2 and Fig. 3, as follows.

The circuit of this embodiment mode can use any input pin not already in use in the test mode; in other words the input pins are used for dual purposes. 40 designates an input/test pad connected to one of the input pins and capable of being used either as an input terminal or test terminal. The input applied via input/test pad 40 enters the source input terminal of an N type transmission gate (transistor) 102, whose gate terminal is connected to a power source voltage VSS. The drain output 104 of transmission gate 102 is connected to the source input of another N type transmission gate 105 and also to another power source voltage VDD via an N type transistor 103. N type transistor 103 and N type transmission gate 105 are connected via their respective gate terminals to the drain output of the gate 105, which in turn is connected via P type transistor 107 to power source voltage VDD.

The gate input of P type transistor 107 is connected to power source voltage VSS so as to operate as a pull-up transistor. The source input of P type transistor 107 is connected to the input of inverter 150 consisting of P type transistor 108 and P type transistor 109, and the output of inverter 150 is connected to the input of inverter 151 consisting of P type transistor 110 and N type transistor 111. The output from inverter 151 is applied to the input terminal of NAND GATE 18 in the same manner as in the Fig. 1 circuit, the output from inverter 150 also being applied to the input terminal of NAND GATE 27. In addition, referring to Fig. 3, input/test pad 40 is connected to inverter 34 to apply a test mode and input signal simultaneously, the inverter 34 being connected via inverter 36 to output 37.

The operation of this embodiment will now be described.

Referring to Fig. 3, during operation in a normal mode of the circuit the signal level applied to pad 40 swings between OV and VDD. N type transmission gate 102 meanwhile is in the off state, and node 106 is pull-up charged to VDD level via P type transistor 107.

Node 104 is charged to VDD-VIN level since N type transistor 103 becomes in the "turn on" state by the voltage of the node 106.

Further, when the output of inverter 150 is "low", the output of inverter 151 becomes "high", such that, as shown in Fig. 3, the input of NAND GATE 27 is interrupted to put NAND GATE 18 into an operational state and cause clock input 1 to make octal frequency division operation for a normal operation as shown in Fig. 4(1). In this mode, test input/test pad 40 is used as an input terminal.

On the other hand, when the state of pad 40 is lowered to -SV level, output 37 from the input is at "low" level and makes N type transmission gate 102 to be at "turn-on" state such that node 104 discharges and turns on N type transmission gate 105 to discharge node 106 and keep it at "low" level. Consequently, output of inverter 150 becomes "high" state and output of inverter 151 becomes "low".

NAND GATE 18 is then interrupted so as not to accept clock signals and NAND GATE 20 is also interrupted from input. On the other hand, NAND GATE 27 is made conductive so as to accept clock input 1 via inverters 2,25 and further apply it via NAND GATE 20 to clock terminal CK of toggle flip flop 29 so as to execute a desired test mode function, as in Fig. 4(3).

To summarise, therefore, the present invention can provide an input circuit for executing test modes which eliminates the use of extra exterior pins separately required until now, by using existing in-place pins for dual purposes. The circuit includes a P type transistor and an N type transistor for controlling the charge voltages of respective nodes and two inverters for controlling NAND GATEs. The invention is advantageous in that it employs existing pins instead of using separate additional test pins for executing test modes and thus reduces the number of exterior pins required. This has the effect of reducing the production cost for chip assemblies and simplifying keyboard constructions with further production cost reduction.

It will be understood that although in the above example, the input circuit of the present invention was applied to an octal ripple counter, the present invention may in general also be applied to several other types of logic circuit.

Claims (9)

CLAIMS:

1. An input circuit for executing a test mode, comprising an input/test pad (40) common for an input terminal and test input terminal, a first transistor (107) for controlling the voltage of a node (106) according to signal levels of inputs from the pad (40), a second transistor (103) for controlling the voltage of said node (106), transmission gates (102,105) for controlling nodes respectively according to input signal levels from the pad (40), and a first inverter (150) for inverting the voltage at said node (106) and applying it to a second inverter (151) and to a first logic gate (27) to control the logic gate (27), the second inverter (151) inverting the output of the first inverter (150) and applying it to the input terminal of a second logic gate (18) to control the same, whereby the number of separate exterior pins required for test modes may be reduced.

2. An input circuit as claimed in claim 1, wherein the first transistor (107) is a p-type transistor.

3. An input circuit as claimed in claim 1 or 2, wherein the second transistor (103) is an n-type transistor.

4. An input circuit as claimed in claim 1, 2 or 3, wherein the first and second logic gates (27,18) are NAND gates.

5. An input circuit as claimed in any preceding claim, wherein the first inverter is formed by a pair of transistors (108,109).

6. An input circuit as claimed in any preceding claim, combined with a logic circuit for which the test mode is to be executed.

7. An input circuit as claimed in claim 6, combined with a ripple counter as said logic circuit.

8. An input circuit as claimed in claim 6 or 7, wherein both the input circuit and the logic circuit are combined in the same IC, and wherein the input/test pad (40) of the input circuit is connected to an ordinary input pin of the IC.

9. An input circuit for executing a test mode, substantially as hereinbefore described with reference to Figures 2 to 5 of the accompanying drawings.