JPH0955648A - Timer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a timer conducting tests for each of plural stage of frequency divider circuits in a short time with a simple operation. SOLUTION: A changeover circuit 14a is provided between frequency divider circuits 11, 12 and a changeover circuit 14b is provided between frequency divider circuits 12, 13. When time count of the frequency divider circuit 11 by a test signal is finished, an output signal of the frequency divider circuit 11 actuates a 1st stage of the frequency divider circuit 12 and when the operation is normal, a high frequency test signal from a pre-stage frequency divider circuit 5 is directly inputted to the frequency divider circuit 12 by the changeover circuit 14a in place of the output signal of the frequency divider circuit 11 to test the frequency divider circuit 12. When the test count of the frequency divider circuit 12 is finished, an output signal of the frequency divider circuit 12 operates a first stage of the frequency divider circuit 13 and when the operation is normal, a high frequency test signal from the pre-stage frequency divider circuit 5 is directly inputted to the frequency divider circuit 13 by the changeover circuit 14b in place of the output signal of the frequency divider circuit 12 to test the frequency divider circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer device, and more particularly to a timer device that performs a time counting operation for a long time.

[0002]

2. Description of the Related Art Some timer devices, such as a timer device for an electronic mosquito coil, perform a long time counting operation such as 12 hours. In order to perform the test operation of the timer device that performs such a long time counting operation in a short time, a high frequency oscillator is initially prepared separately, and a test signal from this high frequency oscillator is input to the timer device to perform the test operation. Was going on. However, this method requires a high-frequency oscillator separately, which raises the problem that the operation cost of the clock test increases, and in order to solve this problem, a method of deriving a high-frequency test signal from a timer device is used. There is.

FIG. 4 is a block diagram showing the structure of a conventional timer device. In this timer device, during a normal time counting operation, the output signal of the oscillator 4 is frequency-divided by the prescaler circuit 5 connected to the output terminal of the oscillator 4 to obtain the time counting signal. This clock signal is input to one input terminal of the AND circuit 1 connected to the output terminal of the prescaler circuit 5. At this time, the logical value of the test activation signal DST input to the test terminal t1 is “0”, and the test activation signal DST becomes a logical value “1” via the inverter 6,
It is input to the other input terminal of the AND circuit 1. As a result, the clock signal is input to one input terminal of the OR circuit 3 connected to the output terminal of the AND circuit 1. On the other hand, the logical value "1" is input to one input terminal of the AND circuit 2 in which one input terminal is connected to the intermediate frequency dividing terminal t2 of the prescaler circuit 5.
The test start signal DST is input, and the logical value of the signal at the output terminal of the AND circuit 2 becomes "0". For this reason, the timer circuit 7 connected to the output terminal of the OR circuit 3 receives the clock signal, and the normal clock operation is performed.

Further, during the timing test operation, the logical value of the test activation signal DST input to the test terminal t1 becomes "1", so that the logical value of the signal at the input terminal of the AND circuit 1 is "0". Then, the logical value of the signal at the output terminal of the AND circuit 1 becomes "0". At this time, AND circuit 2
Since the logical value of the signal at the other input terminal of the signal is "1", the high frequency test signal ST from the intermediate frequency dividing terminal t2 becomes
It passes through the AND circuit 2 and the OR circuit 3, and the timer circuit 7
And the test operation of the timer circuit 7 is performed.

[0005]

According to the above-mentioned conventional timer device, the test operation of the timer circuit 7 can be performed by the test signal taken out from the intermediate frequency dividing terminal t2 of the front frequency dividing circuit 5. Although it is not necessary to separately provide a high-frequency oscillator, in a long-time timer device, even if the input is performed with a high-frequency signal, the inspection time is long and further shortened. In order to solve this, even if the frequency dividing circuit is divided into several pieces and a switching circuit as shown in FIG. 4 is provided, the malfunction of the switching circuit causes the timer circuit 7 to operate normally, resulting in a failure. Since it is judged to be normal when it is judged or when only the high frequency signal can be passed, there arises a problem that the operation check of the switching circuit must be performed.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a timer device capable of performing a test operation in a short time for each of a plurality of frequency divider circuits by a simple operation. To provide.

[0007]

In order to achieve the above-mentioned object, the present invention is a timer device comprising a plurality of frequency divider circuits and sequentially performing an operation test of each of the frequency divider circuits.
When a signal that has passed through the divider circuit at the previous stage is received during test operation, the signal is input to the divider circuit at the next stage, and it is determined whether at least the divider unit at the first stage of the divider circuit operates normally. And a switching circuit for switching.

Further, the above switching circuit inputs a signal having a higher frequency than that signal to the frequency dividing circuit of the next stage in place of the signal which has passed through the frequency dividing circuit of the preceding stage when it is determined to be normal.

According to the timer device of the present invention, during a test operation, a signal which has passed through the frequency dividing circuit at the first stage and has been subjected to the frequency dividing action is input to the switching circuit, and then the switching circuit causes the frequency dividing circuit at the next stage to further. Is entered. Then, in the frequency dividing circuit in the next stage, a normal frequency dividing operation is performed. At this time, for example, it is determined whether or not the output of the frequency dividing unit in the first stage is fed back to the switching circuit and operates normally. . Thereafter, each frequency divider circuit is sequentially tested in the same procedure. Further, from the switching circuit, when it is determined that the signal is normal, the signal that has passed through the frequency dividing circuit at the previous stage is switched to a signal having a higher frequency than the signal and input to the frequency dividing circuit at the next stage, and high-speed test operation is performed. .

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a configuration of an embodiment of a timer device according to the present invention, and FIG. 2 is a circuit diagram showing a configuration of the present embodiment.

As shown in FIG. 1, this timer device has a 45
An oscillator 4 that outputs an oscillation signal of 0 kHz, a prescaler circuit 5, three frequency divider circuits 11, 12, 13 and a switching circuit 1
The timer circuit 10 includes 4a and 14b, and a changeover switch 15.

A prescaler circuit 5 is connected to the oscillator 4, and the prescaler circuit 5 outputs a clock signal of 30 Hz in the normal mode and a test signal ST of 1800 Hz in the test mode. The changeover switch 15 is held in the off state in the normal mode, and is kept in the on state in the test mode.

The frequency dividing circuits 11, 12 and 13 include a circuit in which a plurality of flip-flops 16 are connected in series, and divide the clock signal by 1/162, 250 and 32, respectively, and divide it from the output terminal. It is configured to output the measured time signal.

The switching circuit 14a includes a flip-flop 1
It is composed of a 7-input and 2-input NAND circuits 18a, 18b, 18c and a 2-input AND circuit 19. NAND circuit 18
a and one input terminal of the AND circuit 19 is an input terminal T
4 and the output terminal of the AND circuit 19 is connected to the C terminal of the flip-flop 17. The Q terminal of the flip-flop 17 is connected to the other input terminal of the NAND circuit 18a, the (/ Q) terminal of the flip-flop 17 is connected to one input terminal of the NAND circuit 18b, and the output terminals of the NAND circuits 18a and 18b are connected. It is connected to both input terminals of the NAND circuit 18c. Then, the switching circuit 14
b has the same configuration as the switching circuit 14a except that one input terminal of the NAND circuit 18b is connected to the output terminal of the frequency dividing circuit 12.

Further, the NAND circuit 18 of the switching circuit 14a.
The output terminal of c is connected to the C terminal of the first-stage flip-flop 16 of the frequency dividing circuit 12, and the Q terminal of this first-stage flip-flop 16 is connected to the other input terminal of the AND circuit 19 of the switching circuit 14a. . The D terminal and (/ Q) terminal of the first stage flip-flop 16 are connected to each other, and this (/ Q) terminal is connected to the C terminal of the next stage flip-flop 16.

Similarly, the NAND circuit 18 of the switching circuit 14b.
The output terminal of c is connected to the C terminal of the first-stage flip-flop 16 of the frequency dividing circuit 13, and the Q terminal of this first-stage flip-flop 16 is connected to the other input terminal of the NAND circuit 19 of the switching circuit 14b. . The D terminal and (/ Q) terminal of the first stage flip-flop 16 are connected to each other, and this (/ Q) terminal is connected to the C terminal of the next stage flip-flop 16.

The changeover circuits 14a and 14b receive the output signal of the changeover switch 15 and operate in the normal mode when receiving the output signal in the off state, and operate in the test mode when receiving the output signal in the on state.

The basic operation of this embodiment having such a configuration will be described with reference to FIG. In this embodiment,
In the normal timekeeping operation mode in which the changeover switch 15 is held in the off state, the timekeeping signal output from the prescaler circuit 5 is passed from the frequency divider circuit 11 through the changeover circuit 14a as shown in FIG. 3 (a). Is input to the frequency dividing circuit 12 and then to the frequency dividing circuit 13 via the switching circuit 14b, and the timer circuit 10 including the frequency dividing circuits 11, 12 and 13 performs the time counting operation. The frequency dividing circuits 11, 12 and 13 output respective clock signals, which are used to control, for example, the ignition of the electronic mosquito coil or the stop of the operation.

Further, during the test mode operation in which the changeover switch 15 is held in the ON state, the high frequency test signal ST from the prescaler circuit 5 is, as shown in FIG.
Input to the frequency dividing circuit 11 and the switching circuits 14a and 14b,
Although the frequency dividing circuit 11 has received the frequency dividing action, the signal is divided by the frequency dividing circuit 12.
Is input to In the frequency dividing circuit 12, the result of the first stage operated based on the output signal of the frequency dividing circuit 11 input via the switching circuit 14a is fed back to the switching circuit 14a. In the switching circuit 14a, it is determined whether or not the fed-back signal operates normally. When it is determined that the feedback signal is operating normally, the output signal of the frequency dividing circuit 11 is replaced by the pre-division signal. Circuit 5
The high frequency test signal ST output from the frequency divider circuit 12
Is input to Then, the frequency dividing operation is performed based on the high frequency test signal ST, and the frequency-divided signal is output from the frequency dividing circuit 12 to the switching circuit 14b.

The frequency dividing circuit 12 input to the switching circuit 14b
The output signal of is input to the frequency dividing circuit 13, and the frequency dividing circuit 13
Then, the frequency dividing circuit 12 inputted through the switching circuit 14a
The result of the first stage operated based on the output signal of the switching circuit 1
Returned to 4b. In the switching circuit 14b, it is determined whether or not the fed-back signal operates normally. If it is determined that the feedback signal is operating normally, the output signal of the frequency dividing circuit 12 is replaced by the pre-division signal. The high frequency test signal ST output from the frequency dividing circuit 5 is input to the frequency dividing circuit 13. Then, the frequency dividing operation is performed based on the high frequency test signal ST, and the signal subjected to the frequency dividing operation is output as the output test signal.

The operation of this embodiment will be described in more detail with reference to FIG. [Timekeeping Operation] In the timekeeping operation, first, the timekeeping operation is performed in the frequency dividing circuit 11 based on the timekeeping signal. At this time, the logical value of the signal at the input terminal of the AND circuit 19 of the switching circuit 14a is "0", the logical value of the signal at the output terminal of the AND circuit 19 is "0", and the logical value of the C terminal of the flip-flop 17 is The logical value of the signal is “0”, the logical value of the signal of the Q terminal is “0”, and the logical value of the signal of the (/ Q) terminal is “1”.

Therefore, while the logical value of the signal at the output terminal of the frequency dividing circuit 11 is "0", the logical value of the signal at one input terminal of the NAND circuit 18b of the switching circuit 14a is "0".
Since the logical value of the signal of the other input terminal is "1", the logical value of the signal of the output terminal of the NAND circuit 18b maintains "1". On the other hand, the logical values of the signals at the input terminals of the NAND circuit 18a of the switching circuit 14a are all "0".
The logical value of the signal at the output terminal of the NAND circuit 18a is "1". Therefore, since the input terminal of the NAND circuit 18c of the switching circuit 14a has a logical value of "1", the logical value of the signal at the output terminal of the NAND circuit 18c is "0".

From this state, the clock signal is counted up by the frequency dividing circuit 11, and when the logical value of the signal at the output terminal of the frequency dividing circuit 11 becomes "1", the first signal of the NAND circuit 18b of the switching circuit 14a is changed. The logical value of the signal at the input terminal of
It changes from "0" to "1", and the logical value of the signal at the output terminal of the NAND circuit 18b changes from "1" to "0". Therefore, the logical value of the signal at the output terminal of the NAND circuit 18c of the switching circuit 14a changes from "0" to "1", and the clock signal passing through the frequency dividing circuit 11 is input to the frequency dividing circuit 12. The clocking operation of the frequency dividing circuit 12 is started.

Also in the switching circuit 14b, the same operation as the operation of the switching circuit 14a with respect to the frequency dividing circuit 12 is performed with respect to the frequency dividing circuit 13, and the clock signal passing through the frequency dividing circuit 12 is
This is input to the frequency dividing circuit 13, and the time counting operation of the frequency dividing circuit 13 is started.

[Test Timekeeping Operation] During the test timekeeping operation, the test signal ST from the prescaler circuit 5 is input to the frequency divider circuit 11 and the test timekeeping operation in the frequency divider circuit 11 is started, and at the same time the test signal ST ST is a switching circuit 14a, 1
4b is input. By the test signal ST, the logical value of the signal of one input terminal of the AND circuit 19 of the switching circuit 14a becomes "1", but the signal of the other input terminal (the Q terminal of the flip-flop 16 at the first stage of the frequency dividing circuit 12). Output signal) is "0", and the signal at the output terminal of the AND circuit 21 is "0". Therefore, the logical value of the signal at the C terminal of the flip-flop 17 of the switching circuit 14a is "0", the logical value of the signal at the Q terminal is "0", and the logical value of the signal at the (/ Q) terminal is "1". Has become.

Therefore, the logical value of the signal at one input terminal of the NAND circuit 18a of the switching circuit 14a becomes "1", the logical value of the signal at the other input terminal becomes "0", and the signal at the output terminal of the NAND circuit 18a becomes. Has a logical value of "1". The logical value of the signal at one input terminal of the NAND circuit 18b of the switching circuit 14a is "0" unless the test timing operation of the frequency dividing circuit 11 is completed, and the logical value of the signal at the other input terminal is " 1 ". For this purpose, the NAND circuit 18b
The logical value of the signal at the output terminal of is 1 unless the test timing operation of the frequency dividing circuit 11 is completed. Therefore, the logical value of the signal at the input terminal of the NAND circuit 18c of the switching circuit 14a is "1", and the logical value of the signal at the output terminal of the NAND circuit 18c is "0".

From this state, when the test timing operation in the frequency dividing circuit 11 is completed and the counted-up signal is outputted from the frequency dividing circuit 11, the NAND circuit 1 of the switching circuit 14a.
The logical value of the signal of one input terminal of 8b changes from "0" to "1", and the logical value of the signal of the output terminal of the NAND circuit 18b changes from "1" to "0". Therefore,
The logical value of the signal at the output terminal of the NAND circuit 18c of the switching circuit 14a changes from "0" to "1", and at the same time when the test timing operation in the frequency dividing circuit 11 ends, the test signal ST changes to
It is directly input to the frequency dividing circuit 12 via the NAND circuit 18a of the switching circuit 14a, and the test timing operation is started by the output signal of the frequency dividing circuit 11 in the frequency dividing circuit 12.

Since the logical value of the signal at the C terminal of the first stage flip-flop 16 of the frequency dividing circuit 12 is "1", the logical value of the signal at the Q terminal of the first stage flip-flop 16 becomes "1". AND circuit 19 of switching circuit 14a
Is input to the other input terminal of the AND circuit 19 and the output of the AND circuit 19 becomes a logical value "1" and is input to the C terminal of the flip-flop 17. As a result, the logical values of the signals at the Q terminal and (/ Q) terminal of the flip-flop 17 are inverted, and it is confirmed that the first-stage flip-flop 16 operates normally, and at the same time, the output signal of the frequency dividing circuit 11 is output. Instead, the high frequency test signal ST of the prescaler circuit 5 is input to the divider circuit 12, and the test operation is continued.

The operation of the switching circuit 14b with respect to the frequency dividing circuit 13 is the same as the operation of the switching circuit 14a with respect to the frequency dividing circuit 12, and when the test timing operation in the frequency dividing circuit 12 is completed, the switching operation of the switching circuit 14b is performed. , Divider circuit 13
The test signal from the prescaler circuit 5 to the switching circuit 14b.
Is directly input to the frequency dividing circuit 13 via the NAND circuit 18a, and the test time counting operation is started by the test signal ST in the frequency dividing circuit 13.

As described above, according to the present embodiment, at the time of the test timing operation of the timer circuit 10 based on the test signal, the test timing operation of the first stage frequency divider circuit 11 is first performed by the test signal from the prescaler circuit 5. When the test timing operation of the frequency dividing circuit 11 is completed, the first stage of the frequency dividing circuit 12 is operated by the output signal of the frequency dividing circuit 11, and if the operation is normal, the output signal of the frequency dividing circuit 11 is replaced. A high-frequency test signal is input to the frequency dividing circuit 12 to perform a test time counting operation of the frequency dividing circuit 12, and similarly, after the test time counting operation of the frequency dividing circuit 12 is completed, frequency division is performed using the output signal of the frequency dividing circuit 12. If the first stage of the circuit 13 is operated, and if the operation is normal, a high-frequency test signal is input to the frequency dividing circuit 13 instead of the output signal of the frequency dividing circuit 12 to perform the test timing operation of the frequency dividing circuit 13. Because I did If, using the electronic mosquito coil, each dividing circuit of the timer device for a long time of time counting 11, 12, 13
It is possible to perform the test time counting operation of each of the frequency dividing circuits 11, 12 and 13 accurately and with a significantly reduced test time. Further, since the switching circuits 14a and 14b are integrally connected corresponding to the frequency dividing circuit, the switching circuit 14a
It is not necessary to separately perform an operation test on a and 14b, and it becomes possible to efficiently perform the test timekeeping operation of the timer device with a simple operation.

In this embodiment, the frequency dividing circuit 12,
Based on the signal returned from 13, it is determined whether or not the operation of the frequency division unit in the first stage is normally performed, and if normal, the high frequency test signal from the prescaler circuit 5 is input. Although it is configured to perform the test frequency dividing operation, it is not limited to this, a high frequency test signal is supplied from the outside, or a high frequency test signal having a different frequency for each stage is supplied. Various embodiments are possible.

[0032]

As described above, according to the timer device of the present invention, the operation test of the long-time operation timer device is performed.
This can be efficiently performed in a short time for each frequency dividing circuit in each stage.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is a diagram illustrating the principle of the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional timer device.

[Explanation of symbols]

 4 ... Oscillator 5 ... Prescaler circuit 10 ... Timer circuit 11, 12, 13 ... Frequency divider circuit 14a, 14b ... Changeover circuit 15 ... Changeover switch 16, 17 ... Flip-flops 18a, 18b, 18c ... NAND circuit 19 ... AND circuit

Claims (2)

[Claims] 1. A timer device comprising a plurality of stages of frequency divider circuits for sequentially performing an operation test of the frequency divider circuits of the respective stages, wherein when a signal passed through a frequency divider circuit of the preceding stage is received during a test operation, A timer device having a switching circuit for inputting the signal to a frequency dividing circuit of a stage and determining whether or not at least a frequency dividing unit at a first stage of the frequency dividing circuit operates normally. 2. The switching circuit inputs a signal of a frequency higher than the signal to the frequency dividing circuit of the next stage in place of the signal which has passed through the frequency dividing circuit of the preceding stage when it is determined to be normal. Timer device.