JPS6384123A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide equivalent effect without using a special intrinsic gettering (IG) wafer only applying a low temperature heat treatment of 600-90 deg.C newly after providing a deep impurity diffused layer. CONSTITUTION:A hole 24 is opened in an SiO2 film 23 on a p-type Si substrate 21, and P ions are implanted. P is thermally diffused in O2/N2 = 1/5 to form an N-type well 27. At this time O2 near the surface of the substrate is externally diffused to obtain a no-defect layer 22. Then, a low temperature heat treatment of 700 deg.C is executed at O2/N2 = 1/5, O2 in the substrate is precipitated to form a fine nucleus in high concentration. Thereafter, a CMOSFET is formed as usual. The substrate 21 is heat treated several times at 900-1000 deg.C during this period, and nucleus 28 is generated at each time to generate O precipitate having gettering capacity. As a result, metal impurities are gettered to the last of the steps of manufacturing an element. Thus, a normal wafer may be employed without using an expensive IG wafer. Therefore, a cost is reduced, and a semiconductor device having high reliability is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention 1 (Technical Field of the Invention) The present invention relates to a method for manufacturing a semiconductor device having a deep impurity diffusion region, and in particular, to a method for manufacturing a semiconductor device having a deep impurity diffusion region, and in particular to a method for manufacturing a semiconductor device having a deep impurity diffusion region. sic G e
This relates to a manufacturing method for enhancing the effect of tttering (hereinafter referred to as IG).

(Prior Art) Si (silicon) wafers used as substrates for semiconductor devices contain impurities, albeit in small amounts, and may become contaminated or have crystal defects introduced during the manufacturing process. These defects have various effects on device processes and device characteristics.

Conventionally, metal contamination and the like during the manufacturing process of semiconductor devices have been removed using a so-called phosphorus getter using phosphor glass (P2O3).

Recently, IG has been used in addition to phosphorus getter and the like. FIG. 5 is an example of a semiconductor device (NMO8) using an IG wafer.

A semiconductor substrate (wafer) 1 has a defect-free layer 2 with a width A near the surface and a defect layer made of oxygen precipitates with a width B inside the substrate. The metal impurities 6 in the surface layer are taken in and fixed by the oxygen precipitates 5 during the manufacturing process, and are removed from the element formation region. Note that 3 is the Sio2 film, 4
7 is a polycrystalline silicon electrode, and 7 is an aluminum electrode.

Normally, IG wafers are made by heat-treating a mirror-finished wafer 1 at 1100°C or higher to reduce oxygen in the surface layer of the semiconductor substrate by outward diffusion, as shown in FIG.
Figure 6(a)) and its complex at 600℃~9
Heat treatment is performed at a heat treatment temperature of 00°C to remove oxygen precipitate nuclei 8.
(Fig. 6(b)). Also, Figure 6 <
There is also an IG wafer whose surface layer is mirror-polished 9 after the completion of the process in (b) (FIG. 6(C)). Or, as shown in Fig. 6(b'), the wafer shown in Fig. 6(C) has 9
IG wafer (Fig. 6 (d)
)) is also available.

(Problems to be Solved by the Invention) The above-mentioned IG wafer is 1.5 times more expensive than a normal wafer.
5 to 2.5 times higher. DRAM
When using this IG wafer in memory products such as (andom access memory), the manufacturing process accounts for a very large proportion of the product price, and even though IG has an effect, it is difficult to actually use it. Ta.

It is an object of the present invention to solve the problems of the prior art and to provide a method for manufacturing a semiconductor device that is inexpensive and can provide the same IG effect as the conventional IG wafer without using an expensive conventional IG wafer. .

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention relates to a method for manufacturing a semiconductor device having a deep impurity diffusion region, in which a method for manufacturing a semiconductor device having a deep impurity diffusion region is performed. By simply applying low-temperature heat treatment at 600°C to 900°C to the new material, it is possible to obtain the same IG effect as the conventional special IG wafer without using it.

For example, in the manufacturing process of 0MO8 (complementary MO8), a P-type or N-type deep diffusion region (generally referred to as a well) is formed in a semiconductor substrate at the initial stage, and a semiconductor element is built into the region. Since this diffusion step is usually performed at a high temperature of 1100° C. or higher, a defect-free layer with an extremely low oxygen concentration is automatically formed in the element formation region near the substrate surface by outward diffusion of supersaturated M elements. After forming this deep diffusion region, in the present invention, low-temperature heat treatment at 600°C to 900°C is performed.

As a result, the supersaturated oxygen inside the substrate is precipitated, forming a large number of extremely minute nuclei of oxygen precipitates inside the substrate. In the subsequent manufacturing process J3, this substrate undergoes several heat treatment steps at 900° C. to 1000° C., such as forming a gate oxide film. In this heat treatment process, the aforementioned nuclei grow into oxygen precipitates having gettering ability, which become bookring centers and take in metal impurities from the substrate. The substrate on which the nuclei have been formed generates new oxygen precipitates each time it is subjected to the heat treatment process, so that the IG effect is always obtained during the device manufacturing process.

The formation of oxygen precipitates depends on the distribution of their nuclei, the oxygen concentration in the semiconductor substrate, etc., but as a result of trials, the oxygen concentration in the semiconductor substrate is at least 1.3 x 101018ato/cm
' is desirable. If the oxygen concentration in the substrate is too low, it will be difficult to form a sufficient number of oxygen precipitates. Note that oxygen′
The a degree is the concentration of interstitial atoms, and the infrared absorption coefficient α (all-
'), Q L= (X X 4.81 X 101
This is the value obtained from 7atolIls/cm' (hereinafter, the oxygen concentration according to this definition will be expressed as OL).

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.
Figure 1 shows complementary MO3 random access memory (CM
FIG. 3 is a cross-sectional view showing a manufacturing process when the present invention is applied to manufacturing an O8' RAM.

The silicon substrate (wafer) 21 used had a diameter of 125 m.
m, specific resistance 4-6Ω・CRI, interstitial oxygen concentration (Ot
) is (1,4~1.8) X1X1018ato /
It is a c+n3 P type substrate. As shown in FIG. 1(a), an oxide film (SiO2 film) 23 is formed on this substrate 21, and then, as shown in FIG. Diffusion window 24 for well formation
is opened and a predetermined donor impurity P (phosphorus) is ion-implanted. Next, as shown in Figure (C), heat treatment is performed at 1200°C for 180 minutes in an atmosphere of 02/N2 = 115 to diffuse phosphorus, and the oxygen near the substrate surface is diffused to a depth of about 10 cm. It is released by diffusion, its concentration becomes extremely small, and a defect-free layer 22 is formed on the substrate surface. Next, as shown in FIG. 4(d), heat treatment is applied at 700° C. for 36 hours in an atmosphere of 02/N2=115. This low-temperature treatment causes oxygen in the substrate to precipitate, and very small nuclei 28, estimated to be several to tens of seconds in size, are formed at a high density.

After this low-temperature heat treatment, a P-channel type MOS is installed in the N-well and an N-channel type MOS is installed in the P-type substrate using the usual method.
The FET is formed, but during the manufacturing process, the substrate 2
No. 1 undergoes several heat treatments at 900°C to 1000°C.
Each time this heat treatment is performed, the nuclei 28 grow and oxygen precipitates with gettering ability are generated. For this reason, gettering of impurities and the like is performed until the end of the device manufacturing process.

After manufacturing 0MO8 DRAM by the method described above, separate this I-8 (when the main surface of the M plate is the ('100) plane,
The g-opening plane is (110) plane), and the formation of oxygen precipitates on the male-opening plane is examined using a light etching solution (HF (49%)).
:60n+l, 1-INO3 : 60m1, C
u NO3: 2g, Cr 03 (5 mol)
:30a+1,OH3Coo)-1(100%)
: 60 ml, H 2 0 : 60 ml) for 90 seconds and then observed. Figure 2 shows the amount of oxygen precipitates expressed as the number of etch bits per unit area of the open surface. Figure 3 shows the defect-free layer near the substrate surface (the width A of Figure 1(c) 22 is 30 mm).
A defect-free layer of ~60 μI is formed. The larger the oxygen concentration (0) in the substrate, the smaller the defect-free layer width becomes.
From FIG. 2 and FIG. 3, in order to obtain the IG effect according to the present invention, the oxygen concentration (OL) in the substrate must be 1.3 x 10" at
It can be seen that it is desirable that r be at least ols /cn+', and that the upper limit thereof is determined by the width of the defect-free layer required as the element forming region.

FIG. 4 shows the results of observing the tendency of memory retention time to deteriorate when the product was left at high temperature (200° C.). The horizontal axis shows the unused time (hours), and the vertical axis shows the ratio of the memory retention time after the unused time to the memory retention time of the 0MO8 DRAM in J3 at the beginning of the unused time 0. In this experiment, for comparison, a conventional wafer was used (Δ mark in Fig. 4), a conventional IG wafer was used ( I followed O mark). Compared to devices made using normal wafers, devices made using the method according to the present invention and devices made using conventional IG fabrication have a smaller tendency to deteriorate;
It can be seen that there is no difference from that due to G-way 8.

In the above embodiments, the semiconductor device is 0MO8, and the deep impurity diffusion region is a P-well or an N-well, but the present invention is not limited to this.

For example, the present invention can of course be applied to a manufacturing process of a semiconductor device in which a heat treatment step of 1100° C. or higher is performed at a relatively early stage of the manufacturing process, such as a semiconductor device having a bonding type element isolation layer.

[Effects of the Invention] According to the semiconductor device manufacturing method of the present invention, there is no need to apply special heat treatment or use mirror-polished wafers before the device manufacturing process, and the wafer price is the same as that of regular wafers. , it becomes 2/3 to 1/2 of the conventional IG raw speed.

Furthermore, as is clear from the results of the above-mentioned examples, the device manufactured by the method of the present invention is not inferior to the conventional IG wafer in terms of IG effect, and has no effect on improving memory retention time or reliability. It's large.

As described above, according to the manufacturing method of the present invention, the expensive conventional I
I do not use a G wafer, but I
The G effect can be obtained, and a semiconductor device with improved product yield and reliability can be manufactured.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of the manufacturing process of a semiconductor device according to the present invention, and FIG. 2 is a graph showing the relationship between the amount of oxygen precipitates formed in a silicon wafer according to the present invention and the oxygen concentration in the wafer. , Fig. 3 is a graph showing the relationship between the defect-free layer width formed in a silicon wafer according to the present invention and the oxygen concentration in the wafer, and Fig. 4 shows the tendency of deterioration of memory retention time due to high temperature storage for each method. FIG. 5 is a cross-sectional view of an element using a conventional IG wafer, and FIG. 6 is a cross-sectional view showing the manufacturing process of a conventional IG wafer. 1.21... Semiconductor substrate, 2.22... Defect-free layer, 3.23... 5i02 film, 5... Oxygen precipitate,
6... Metal impurity, 8.28... Oxygen precipitate nucleus, 27... N well. Figure 2 Chest 3 Height 54L (200'C) 1! Kin (hourly) Figure 4 # Vermilion Figure 6

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device selectively having a deep opposite conductivity type impurity diffusion region in a semiconductor substrate of one conductivity type, comprising: 1
A method for manufacturing a semiconductor device, comprising the step of performing heat treatment at 600°C to 900°C after forming the deep opposite conductivity type impurity diffusion region at a temperature of 100°C or higher. 2 The oxygen concentration of the one conductivity type semiconductor substrate is at least 1
．． The method for manufacturing a semiconductor device according to claim 1, wherein the rate is 3×10^1^8 atoms/cm^3. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the semiconductor device is a CMOS, and the deep opposite conductivity type impurity diffusion region is a P-well or an N-well.