JPS6382535A - Channel device - Google Patents

Abstract

PURPOSE:To independently carry out a main memory access according to a sub-channel control in plural input and output controls by performing the main memory access through a sub-channel information area in a sub-channel memory. CONSTITUTION:Input and output starting instructions outputted to a channel device 10 from a CPU includes a function information indicating a processor communication, an input and output instruction type code, a channel number, a sub-channel number and a sub-channel control information address, which are respectively set to input and output registers 21, 22, 23. A sequence control circuit 31 sets a memory address corresponding to the sub-channel number to a register 32 based on the function information. Then, response information indicating that the input and output instruction is received is set to the register 23 and the information is transferred to the CPU through a system bus 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention J (Field of Industrial Application) The present invention relates to a channel device that performs input/output control of a plurality of subchannels, and particularly relates to a main memory access method associated with subchannel control.

(Prior Art) When this type of channel device is given one input/output activation command from the CPU, it processes the input/output activation command (i.e., the
It accepts an input/output activation command from the PU and executes a process of fetching subchannel control information from the main memory area specified by the command. Now, in conventional channel devices, even though there are multiple input/output controls under the channel and multiplex control is required, main memory access accompanying subchannel control is performed by using address registers and data registers common to each subchannel in the channel device. It was executed by setting the internal microprocessor. For this reason, C
Access to main memory such as subchannel control information (channel control t11 words) by input/output commands from the PU must also be executed by the microprocessor' with exclusion for multiplex control, and multiple input/output controls are required. There was a problem of lack of independence.

In addition, when accessing subchannel control information, the microprocessor performs input/output control (subchannel control).
Address registers must be set every time after decoding an input/output activation command in units of 1 to 1000, which poses a problem that adversely affects the responsiveness of input/output activation control.

(Problems to be Solved by the Invention) As described above, in conventional channel devices, main memory access accompanying subchannel control is performed by a microprocessor using an address register common to each subchannel. lacks independence of input/output control,
In addition, there was a problem in that the input/output activation control lacked high-speed responsiveness.

The present invention has been made in view of the above circumstances, and its purpose is to provide a channel device that can perform main memory access independently for each subchannel associated with subchannel control, and is highly responsive to input/output activation control. It is in.

[Configuration of the invention (Means and actions for solving the problem) In this invention,
A subchannel memory having an independent subchannel information area allocated for each subchannel, first and second address registers for specifying addresses of the subchannel memory, a sequence control circuit, and a microprocessor are provided. When the microprocessor requires main memory access for subchannel input/output control,
The subchannel number that specifies the subchannel to be input/output controlled is set in the first address register, and the storage destination address in the main memory of information related to subchannel control is set in the subchannel information area in the subchannel memory specified by this first address register. , and issues a main memory access request. When a main memory access request is issued from the microprocessor, the sequence control circuit performs main memory access on behalf of the microprocessor using main memory access information written by the microprocessor to the subchannel information area in the subchannel memory. . In addition, when it is necessary to read subchannel control information that describes input/output control contents by an input/output start command from the CPLI, the sequence control circuit sends a subchannel number specifying the input/output control target subchannel to a second address. The main memory access information including the storage address of the subchannel control information in the main memory is written to the subchannel information area in the subchannel memory specified by this second address register, and the written information is used to access the main memory. Perform access. According to the above configuration, main memory access can be performed via the subchannel information area in the subchannel memory prepared for each subchannel, so independence of main memory access is improved, and subchannel control information, etc. Since the main memory access for reading is performed by the sequence control circuit, high-speed response is achieved.

(Embodiment) FIG. 1 shows a block configuration of a channel device according to an embodiment of the present invention. In the figure, 10 is a channel device. The channel device 10 has a system bus 14 consisting of a control bus 11, an address bus 12 and a data bus 13.
It is connected to the. A CPU, main memory, etc. (not shown) are also connected to the system bus 14.

In the channel device 10, 21 is a bidirectional input/output register (IO
R), 22 is a bidirectional input/output register <IOR> used for information input/output with the address bus 12, and 23 is a bidirectional input/output register used for information input/output with the address bus 12. It is a register (IOR). Input/output register 22.
23 is connected to an internal bus 24. A data input/output port D of a subchannel memory 25 is connected to this internal bus 24 .

As shown in FIG. 2, the memory area of the subchannel memory 25 includes a plurality of areas (referred to as subchannel information areas).
It is divided into 26-0 to 26-m. The subchannel information area 26-i (i = ○ to m) is used to store information (referred to as subchannel information) necessary for input/output control of subchannel #i with number 1, Field 27a in which the channel number assigned to the channel device 10 is set; field 27b1 in which the number assigned to subchannel #i (subchannel number) is set;
Field 27 where the storage address in the main memory (referred to as subchannel control information address) of input/output control information (referred to as subchannel control information) of subchannel #i is set.
c. Field 27d1 where a flag (F) indicating that input/output control is in progress for subchannel #l is set; information necessary for main memory access associated with input/output control of subchannel #i (main memory access information) is set; The main memory access information has a field 27e1 and a field 27f in which information read from the main memory (main memory information) is set based on the main memory access information. The main memory access information set in the field 27e includes control information indicating the type of main memory access (distinction between read access/write access, distinction between fullword access/halfword access, etc.), address information, and data (write access). (in case of access). In this embodiment, input/output devices, sessions, transmitting functions, receiving functions of one terminal, etc. that are physically connected to the channel device 10 are treated as subchannels subject to input/output control of the channel device 10. Defined.

Referring again to FIG. 1, 31 is the subchannel memory 2.
5 is a sequence control circuit that executes input/output and system bus procedures for 5. The sequence control circuit 31 is connected to the input/output register 21 and the internal bus 24, and is connected to the address register (AR>32, address line 3).
3 to address port A of subchannel memory 25.
It is connected to the. As shown in FIG. 3, the address line 33A and the internal bus 24 are connected to codes (input/output The input of a FIFO (first-in-first-out) buffer 34 for temporarily storing an instruction type code) and a subchannel number is connected. The FIFO buffer 34 is configured to output a signal to the interrupt line 35 each time the above information is stored. This interrupt line 3
5 is connected to a microprocessor 36 which forms the core of the channel device 10 and performs input/output control requested by the CPU.

The output of the FIFO buffer 34 and the input of an address register (AR) 38 that specifies the address of the subchannel memory 25 are connected to a bus 37 of the microprocessor 36 (hereinafter referred to as the microprocessor bus). The output of this address register 38 is connected to the address line 33. Further, one input/output port of a bidirectional input/output register (IOR) 39 is connected to the microprocessor bus 37, and is mainly used for inputting/outputting information between the subchannel memory 25 and the microprocessor 36. . The other input/output port of input/output register 39 is connected to data input/output port D of subchannel memory 25 and internal bus 24. Also,
Microprocessor 36 is connected to sequence control circuit 31 by control line 40 .

Next, the operation of one embodiment of the present invention will be explained.

It is now assumed that an input/output activation instruction (subchannel input/output activation instruction) targeting subchannel #i with i=1 is output from the CPU onto the system bus 14. This input/output activation instruction includes function information indicating that it is processor communication (here, communication from the CPU to the channel device 10), an input/output instruction type code indicating that it is an input/output activation instruction, a channel number, and a subchannel number. (here 1
) and subchannel control information address.

In this embodiment, among the above input/output activation instructions, function information is stored on the control bus 11 of the system bus 14.
The input/output instruction type code, channel number, and subchannel number are output onto the address bus 12, and the channel control information address is output onto the data bus 13, respectively.

The function information on the control bus 11 is stored in the input/output register 21, the input/output instruction type code on the address bus 12,
The channel number and subchannel number it input/output register 22 are routed, and the channel control information address on the data bus 13 is routed to the input/output register 23, respectively.

If the channel number from the address bus 12 specifies the channel device r1110, the function information is stored in the input/output register 21 by the input enable signal from the channel number decoder (not shown), including the input/output instruction type code, The channel number and subchannel number are set in the input/output register 22, and the channel control information address is set in the input/output register 23, respectively.

The function information set in the input/output register 21 is supplied to the sequence control circuit 31. When the sequence control circuit 31 recognizes communication from the CPU based on this function information, it takes in the subchannel number from the input/output register 22 via the internal bus 24 and stores the subchannel memory address corresponding to this subchannel number in the address register 32. set. Assuming that the size of the subchannel information areas 26-0 to 26-11 is 2n bytes, the address set in this address register 32 is a concatenation of the subchannel number and n-bit data (each bit is 110"). information, and the subchannel number is stored in the subchannel information area 26 in the subchannel memory 25.
The n-bit data indicates an upper address that specifies -1, and a lower address that specifies an offset within the subchannel information area 26-1. By sequentially incrementing the lower addresses, the sequence control circuit 31 converts the channel number and subchannel number in the information set in the input/output register 22 into the subchannel information area 26-1 of the subchannel memory 25 (here, 1-1), the subchannel control information address set in the input/output register 23 is written in the field 27c, and the flag (F) of logic "1111" is written in the field 27d.

Next, since the input/output type code in the information set in the input/output register 22 indicates an input/output activation instruction, the sequence control circuit 31 responds with a response indicating that it has accepted the input/output activation instruction from the CPU. Information input/output register 2
3, and also sets function information indicating that communication is to the CPU in the input/output register 21, and transfers information to the CPU via the system bus 14. That is, the sequence control circuit 31 controls the subchannel memory 25
(subchannel #) to the subchannel information area 26-1 of
When writing subchannel information (related to i), c
The input/output activation command reception returns a response to p-u.

When the sequence control circuit 31 returns a response to the CPU, it inputs the input/output type code in the information set in the input/output register 22 and the subchannel number which is the upper address of the subchannel memory address output from the address register 32. are set in the FIFO buffer 34.

When information is set to this FIFO buffer 34, a signal indicating this is output from the buffer 34. This signal is provided to microprocessor 36 via interrupt line 35, thereby causing an interrupt to microprocessor 36.

Now, after the sequence control circuit 31 has set the above information to the FIFO 34, it reads the subchannel control information from the main memory as described below. That is, the sequence control circuit 31 first controls the subchannel memory 2.
5 subchannel information area 2B-i (here 1=
1) Read the subchannel control information address from field 27c. Then, sequence control circuit 31 generates main memory access information including this subchannel control information address, and writes it into field 27e of subchannel information area 26-1 in subchannel memory 25. Next, the sequence control circuit 31 reads the main memory access information written in this field 27e from the subchannel memory 25, and transfers it to the main memory via the internal bus 24 and the input/output registers 22,23. Accesses the area in main memory specified by the subchannel control information address in the access information. Thereby, sequence control circuit 31 reads subchannel control information for subchannel #1 from the main memory. This subchannel control information is transferred to the channel device 10 via the system bus 14, for example, the data bus 13, and is set in the input/output register 23. Sequence control circuit 31 writes subchannel control information for subchannel #i from the main memory set in input/output register 23 to field 27f of subchannel information area 26-1 of subchannel memory 25. The above is the subchannel information area 2 in the subchannel memory 25.
This is a main memory access caused by the sequence control circuit 31 itself using the information in the field 27e of 6-1 (main memory access information).

On the other hand, when the microprocessor 36 detects an interrupt from the interrupt line 35, it determines whether to write subchannel information to the subchannel memory 25, and writes the subchannel information to the FIFO buffer 3.
The input/output type code set to 4 and the subchannel number are taken in via the microb O processor bus 37. The microprocessor 36 then selects the subchannel number indicated by the subchannel number fetched from the FIFO buffer 34.
The input/output control task of i (here j-1) is set to a ready state. That is, the microprocessor 36 performs processing related to subchannel #1 (input/output control [l
). As a result, if the tasks corresponding to other subchannels are not in the running state, subchannel #1
Input/output control of subchannel #i according to the task corresponding to is started. Furthermore, if there are other tasks that are ready for operation, input/output control is performed according to their priorities. Note that during this input/output control, subchannel control information reading described below is performed.

First, the microprocessor 36 stores the subchannel memory 2
Subchannel information area 2 for subchannel #1 in 5
The start address of the field 27f of 6-1 is set in the address register 38. This address is the subchannel #i for specifying the subchannel information area 26-1.
It consists of concatenated information of the subchannel number of , and an offset (n bits) within the subchannel information area 26-1 for specifying the starting position of the field 27f. Then, microprocessor 36 reads data from subchannel memory 25 while incrementing the lower address (n-bit offset within subchannel information area 26-1) of address register 38. As a result, subchannel control information regarding subchannel #i is sequentially read from field 27f of subchannel information area 26-1 of subchannel memory 25. microprocessor 36
takes in the subchannel control information read from the subchannel memory 25 into an internal memory (not shown) via the input/output register 39 and the microprocessor bus 31. The microprocessor 36 then performs input/output control of the subchannel #i according to the acquired subchannel control information.

As described above, according to this embodiment, the sequence control circuit 31 automatically decodes the input/output activation command and reads out the subchannel control information necessary for executing the command, and the microprocessor 36 performs sequence control. circuit 31
Since preparation for corresponding subchannel control can be made while subchannel control information is read by , high-speed response of input/output activation control is possible.

Now, the subchannel control information taken in from the subchannel memory 25 is transferred to the main memory in which the command specifying the setup operation necessary for input/output control of subchannel #i and the parameters for the setup are stored. It is assumed that it has an inner area destination address. In this case, the microprocessor 36 performs main memory access information writing described below in order to obtain the above parameters from the main memory.

First, the microprocessor 36 stores the subchannel memory 2
Field 27e of subchannel information area 26-1 of No. 5
(i.e., the subchannel number of subchannel #i and the field 27 in the subchannel information area 26-1)
The concatenated address with the n-bit offset address that indicates the start position of 38 (in this case, the starting position of field 27e of subchannel information area 26-1). Next, the microprocessor 36 increments the lower address (n-bit offset within the subchannel information area 2G-1) of the address register 38 and sets the next word of main memory access information in the input/output register 39. , performs the write operation to the sub-channel memory 25 described above. When the microprocessor 36 repeats the above-mentioned 1-setting and finishes writing the main memory access information to the field 27e of the subchannel information area 26-i (here 1=1), the microprocessor 36 sends the control line 40 to the sequence control circuit 31. requests main memory access via

When the sequence control circuit 31 receives a main memory access request from the microprocessor 36, the sequence control circuit 31 first addresses an offset address indicating the start position of the field 27e in the subchannel information area 26-1 of the subchannel memory 25 (this value is stored in the subchannel memory 25). (common to field 27e of any subchannel information area of 25) is set to the lower address field (n bits) of address register 32.
Set to . Next, the sequence control circuit 31 outputs the upper address of the address register 38 at that time (i.e., the subchannel number of subchannel #1) and the address register 3
2 lower address (i.e. subchannel information area 26-1
The sub-channel memory 25 is read accessed using the offset address indicating the start position of the inner field 27e, while sequentially incrementing this lower address, and the information written by the microprocessor 36 in the field 27e of the sub-channel information area 26-1 is accessed. Read main memory access information. Next, the sequence control circuit 31 accesses the main memory using the main memory access information read from the subchannel memory 25, and accesses the corresponding data (here, set-up) from the area in the main memory specified by the address information in the information. parameters). Then, sequence control circuit 31 writes the data read from the main memory into field 27f of subchannel information area 26-1 in subchannel memory 25 in response to a request from microprocessor 36.

When the microprocessor 3G learns of the end of the main memory access (main memory read access) from the status notification etc. from the sequence control circuit 31, the microprocessor 3G reads the data (main memory information) written in the field 27f of the subchannel information area 26-1. ) is read via the input/output register 39 and microprocessor bus 37 and set in the internal memory. Then, the microprocessor 36 executes input/output control of subchannel #i by using the data set in this internal memory (here, parameters necessary for the setup operation associated with input/output control of subchannel #1). be able to.

Now, it is assumed that while the microprocessor 36 is executing input/output control of subchannel #i, an input/output activation command targeting another subchannel #j is issued from CPtJ.

The subchannel information area for this subchannel #j is different from that for subchannel #i. Therefore, the subchannel information regarding subchannel #J is deleted by the sequence control circuit 31 in the same manner as in the case of the input/output activation command targeting subchannel #1. The data is reliably written to the subchannel memory 25 without any errors. That is, the channel device 10 can accept another input/output activation command from the CPU even while processing the input/output activation command.

Note that the subchannel information area 26-i (for example, 1-
The flag (F) in 1) is reset when all input/output control according to the subchannel control information specified by the subchannel control information address in the same area is completed.

[Effects of the Invention] As detailed above, according to the present invention, main memory access can be performed via the subchannel information area in the subchannel memory prepared for each subchannel. Increased access independence. In addition, main memory access for reading subchannel control information, etc. in response to an input/output activation command from the CPU can be performed independently from the microprocessor by the sequence control circuit, so the microprocessor prepares for corresponding input/output control during this time. Therefore, high-speed response of input/output activation control is possible.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a channel device according to an embodiment of the present invention, FIG. 2 is a diagram explaining a subchannel information area allocated to the subchannel memory 25 shown in FIG. 1, and FIG. FIG. 3 is a diagram showing the structure of information written to the FIFO buffer 34 shown in the figure. 10... Channel device, 14... System bus, 2
1.22゜23,39...I/O register (10R)
, 25... subchannel memory, 26-0 to 26-
m...Subchannel information area, 31...Sequence control circuit, 32.38...Address register (AR)
, 34... FIFO buffer, 35... Interrupt line, 3G... Microprocessor, 40... Control line. Applicant's agent Patent attorney Takeshi Suzue Hikoshichi 4
116 Figure 1 Figure 2 Diagram m-Input/Output 4~All 1 intelligence) Ricoh 1': 23 Figure

Claims (1)

[Claims] A subchannel memory having a subchannel information area that is an independent area allocated for each subchannel and that can be addressed by a subchannel number indicating the corresponding subchannel, and a first and second subchannel memory that specifies the address of this subchannel memory. 2 address register and the subchannel number that specifies the subchannel to be input/output controlled for main memory access associated with subchannel input/output control, and set it in the first address register. The microprocessor that issues the main memory access request writes main memory access information including the storage destination address in the main memory of information related to subchannel control to the subchannel information area in the channel memory, and the above-mentioned process is performed in response to the main memory access request from this microprocessor. Main memory access is performed using the main memory access information written in the subchannel information area in the subchannel memory specified by the first register, and input/output start commands are received from the CPU and input/output control contents are executed. In order to read the described subchannel control information, a subchannel number specifying the input/output control target subchannel is set in the second address register, and the subchannel information area in the subchannel memory specified by the second address register is set. A channel device comprising: a sequence control circuit for writing main memory access information including a storage address in the main memory of the sub-channel control information into the main memory and accessing the main memory using the written information.