JPS6381972A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the density of integration of transistors by forming a forward bipolar transistor and a reverse bipolar transistor into the same cell. CONSTITUTION:An npn type bipolar transistor Q1 is constituted of an emitter region 8, a base region 6 and a collector region consisting of an silicon epitaxial layer 41 in the lower section of the base region 6, an npn type bipolar transistor Q2 is organized of an emitter region composed of an silicon epitaxial layer 42 in the lower section of a base region 7, the base region 7 and a collector region 9, and the emitter region in Q2 and the collector region in Q1 are connected mutually by a buried layer 2. Accordingly, the density of integration of transistors can be made larger than the forward and reverse npn type bipolar transistors Q1, Q2 are shaped independently in separate cell by approximately twice because Q1 and Q2 are formed in the same cell, and parasitic capacitance CTS with a semiconductor substrate 1 can be minimized because the area of the buried layer 2 per one can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit device having a forward bipolar transistor and a reverse bipolar transistor. It is something.

[Conventional technology]

Cascode-connected differential amplifiers, which are often used as linear IC amplifier circuits, are known (for example, Ohmsha Publishing, November 20, 1975, Semiconductor Circuit Manual, P.
, 1042-1043), the circuit configuration of a part of the differential amplifier circuit is shown in FIG. 2. As shown in FIG. 2, in this cascode-connected differential amplifier, npn type bipolar transistors Q1. Q2 and resistor R1 are connected in series, and an npn bipolar transistor Q3
．． Qa and resistor R2 are connected in series. The resistance R
+.

One end of R2 is connected to the power supply potential VCC.

A constant current source C is connected to the emitters of the transistors Q, ,Q,
8 are connected. In the cascode-connected differential amplifier configured in this way, the transistor Q1.
Signals Vin+ and Vin are applied to the base of Qs, respectively.
2, and the output that amplifies the difference between them is the output signal Vo.
It is obtained as the difference between ut, t, and Vout2. This cascode-connected differential amplifier reduces the Miller capacitance appearing on the input side, thereby reducing the input capacitance and widening the bandwidth of the amplifier. In addition, the second
In the figure, transistor Q2. The base of Q4 has a constant potential v.

is set to .

The inventor studied a cascode-connected differential amplifier using a linear IC. Although the following is not a publicly known technique, it is a technique studied by the present invention, and its outline is as follows.

That is, in the technique studied by the present inventor, a field insulating film is selectively formed in, for example, an n-type epitaxial layer provided on a semiconductor substrate to define a transistor formation region. The transistor formation region in this case is called a cell. This cell is divided into two regions by a field insulating film provided within the cell, and one region is provided with, for example, a P-type base region and, for example, a T-type emitter region. An npn type bipolar transistor is constituted by the emitter region, the base region, and the collector region made of the epitaxial layer below the base region, and the electrode for the collector region of this transistor is taken out from the other region of the cell.

The transistors Q1 to Q4 in FIG. 2 were constructed using four transistors having the above-mentioned configuration.

That is, it was necessary to use four cells to configure a cascode-connected differential amplifier.

[Problem that the invention seeks to solve]

However, when one transistor is formed in one cell in this way, there is a limit to the integration density of the transistors.

An object of the present invention is to provide a technique that can improve the integration density of transistors.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Outline of typical inventions disclosed in this application is as follows.

That is, a forward bipolar transistor and a reverse bipolar transistor are provided in the same cell.

[For production]

According to the above-described means, the area occupied by each transistor can be reduced, so that the integration density of transistors can be improved.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below based on embodiments with reference to the drawings.

In addition, in all the figures, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

As shown in FIG. 1, in the linear IC according to Embodiment I, a buried layer 2 of, for example, an n type and a channel stopper of, for example, a P0 type are formed on the surface of a semiconductor substrate l such as a P type silicon substrate. Region 3 is provided. For example, an n-type silicon epitaxial layer 4 is formed on the semiconductor substrate 1.
A field insulating film 5, such as a SiO2 film, is provided on the side surface of the silicon epitaxial layer 4 and on the surface of the semiconductor substrate 1. Silicon epitaxial layers J separated from each other by this field insulating film 5
&4+, 42 each include, for example, a p-type base region 6.
, 7 are provided, and in these base regions 6 and 7, for example, an n'' type emitter region 8 and collector region 9 are provided respectively.

The silicon epitaxial layers 41 and 42 surrounded by the field insulating film 5 constitute one cell.

An npn bipolar transistor Q1 is constituted by the emitter region 8, the base region 6, and the collector region made of the silicon epitaxial layer 41 below the base region 6, and the emitter region made of the silicon epitaxial layer 42 below the base region 7. ,
The base region 9 and the collector region 9 constitute an npn type bipolar transistor Q2. In addition, code 6
a.

7a is, for example, an R4 type graft base region.

The emitter region of the npn bipolar transistor Q1 and the collector region of the npn bipolar transistor Q1 are connected to each other by a buried layer 2. Here, the transistor Q is called a forward npn-type bipolar transistor, and the transistor Q2, whose emitter region and collector region have a positional relationship opposite to that of the forward npn-type bipolar transistor Q1, is called a reverse npn-type bipolar transistor. call.

These forward and reverse npn bipolar transistors Q! , Q2, forward and reverse npn bipolar transistors Qs, Q4 (not shown) having the same configuration as these transistors Q, , Q2, and resistors R1, R2.
(not shown), the cascode-connected differential amplifier shown in FIG. The silicon epitaxial layer 42 was used for taking out the collector electrode, but in this embodiment, as described above, the silicon epitaxial layer 42 was used to take out the collector electrode in the forward and reverse directions.
pn type bipolar transistor QI.

Since Q2 is provided, these transistors Q1 and Q
The integration density of transistors can be increased approximately twice as compared to the case where transistors 2 and 2 are formed independently in separate cells. Also, in this way, two transistors Q,...
Q, these transistors Q1. Q
The area of the buried layer 2 per transistor can be reduced compared to the case where the buried layer 2 is formed independently in separate cells. Therefore, the parasitic capacitance C between the buried layer 2 and the semiconductor substrate 1 can be reduced. Note that the current amplification factor h+gH of the reverse npn bipolar transistor Q2 is smaller than that of the forward npn bipolar transistor Q, but as shown in FIG. This poses no practical problem since it is used in

On the surface of the silicon epitaxial layer 1fJ4*, 42, an insulation II# film 10, such as a SiO2 film, is provided. This insulating film 10 and the field insulating film 5
An insulating film 11, for example a Si3N film, is provided on the insulating film 10.11, and these insulating films 10.11 have the graft base region 6a, the emitter region 8 and the graft base region 7.
a and the collector region 9, respectively.
124 are provided. For example, a P'' type polycrystalline silicon film 13 is provided on the insulating film 11 and is connected to the graft base regions 6a and 7a through the openings 121 and 123, respectively, so that base extraction is performed. There is. This polycrystalline silicon [13] is covered with an insulating film 14, 15, such as a SiO2 film. For example, an n0 type polycrystalline silicon film 16 is provided on the emitter region 8 and the collector region 9 through the openings 122 and 124. This polycrystalline silicon film 16 is covered with an insulating film 17 such as a SiO2 film and an insulating film 18 such as a Si3N4 film.

These insulating films 17.18 are provided with openings 191-194, and electrodes 20-3 made of, for example, an aluminum film are provided on the polycrystalline silicon film 13.16 through these openings 191-194. .

Next, a method for manufacturing a linear IC according to Example I will be described.

As shown in FIG. 3, first, a buried layer 2 and a channel stopper region 3 are selectively formed on the surface of a semiconductor substrate 1 by, for example, diffusion or ion implantation, and then a silicon epitaxial layer 4 is formed on the semiconductor substrate 1 by, for example, epitaxial growth. The silicon epitaxial layer 4 is formed into a predetermined shape by etching. Next, after forming a field insulating film 5 by selectively thermally oxidizing the side surfaces of this silicon epitaxial layer 4 and the surface of the semiconductor substrate 1, the surface of the active region recessed by this field insulating film 5 is heated, for example. An insulating film 10 such as a 5i02 film is formed by oxidation. Next, after sequentially forming an insulating film 11 such as 5isN+rflI and a polycrystalline silicon film 24 on the entire surface of the field insulating film 5 and the insulating film 10, the surface of the polycrystalline silicon film 24 is thermally oxidized. For example, an insulating film 25 such as a SiO2 film is formed, and on this insulating film 25, for example, Si, N,
26 is formed on the insulation 11, such as a film. Thereafter, a photoresist 27 having a predetermined shape is formed on this insulating film 26.

Next, as shown in FIG. 4, using the photoresist 27 as a mask, the insulating film 26 is etched until side etching occurs. (B) is ion implanted. Note that the portion into which B ions are implanted is indicated by the reference numeral 24a.

Next, after removing the photoresist 27.

Said B ion-implanted by performing annealing
is diffused into the polycrystalline silicon film 24.

Next, by etching the insulating film 25 using the insulating film 26 as a mask until side etching occurs, the insulating film 25 is etched except for the lower part of the insulating film 26, as shown in FIG. Remove.

Next, after removing the insulating film 26 by etching, the insulating film 26 is removed by etching.
5 as a mask, the polycrystalline silicon film 24 is etched. In this case, since the etching rate of polycrystalline silicon is significantly reduced by doping with B, it is possible to selectively etch the portion not doped with B with respect to the portion 24a doped with B using, for example, hydrazine. Utilizing this, the polycrystalline silicon film 24 near the end of the insulating llI 25 is partially etched away to form openings 24b and 24C as shown in FIG.

Next, after the insulating film 25 is etched away, the insulating films 11.10 are sequentially etched away through the openings 24b and 24c, and the openings 121.10 are etched away as shown in FIG.
123 is formed. Next, after etching away the portion of the polycrystalline silicon film 24 that is not doped with B, impurities such as B and BF2 are sequentially ion-implanted into the entire surface to form a P-type base. Regions 6, 7 and, for example, P3 type graft base regions 6a, 7a are formed.

Next, as shown in FIG. 8, after forming, for example, a polycrystalline silicon film 27 on the entire surface, annealing is performed.

As a result, the polycrystalline silicon film 2 doped with B
4a and the graft base regions 6a and 7a, B is diffused into the polycrystalline silicon film 27. In this case, this polycrystalline silicon rJ! The portion of X27 that is in contact with the polycrystalline silicon film 24a and the graft base region 6
B is doped in the portions contacting the insulating films 11 and 6b, but the polycrystalline silicon film 27 on the insulating film 11 is doped with B.
is not doped. Next, by selectively etching the B-doped portions of the polycrystalline silicon film 27 and the undoped portions, only the B-doped portions are left. The crystalline silicon film 24a is patterned into a predetermined shape by etching to form a polycrystalline silicon film 13 having a predetermined shape, as shown in FIG.

Next, as shown in FIG. 10, an insulating film 14 such as a SiO2 film is formed on the entire surface, and an insulating film 2B such as a 5isN4 film is further formed on the insulating film 14. A photoresist 29 having a predetermined shape is formed on the film 2B.
form.

Next, the insulating film 2B is etched using this photoresist 29 as a mask, and the Fn film 14 is further etched using the insulating film 28 left by this etching as a mask, and then the photoresist 29 is removed and the insulating film 2B is etched. 11
Set the state as shown in the figure.

Next, by partially thermally oxidizing the polycrystalline silicon film 13 using the crystalline film 28 as a mask, an insulating layer 1115 such as a SiO2 film is formed as shown in FIG.

Next, after removing the insulating film 2B by etching, the thirteenth
As shown in the figure, a polycrystalline silicon film 16 is formed on the entire surface of the polycrystalline silicon It! 116 is doped with, for example, arsenic (As) by, for example, ion implantation. Next, annealing is performed to remove A in this polycrystalline silicon film 16.
By diffusing s into the silicon epitaxial layer 4, for example, an n4 type emitter region 8 and collector region 9 are formed in the base regions 6 and 7, respectively.

Next, after patterning the polycrystalline silicon f1116 into a predetermined shape by etching, an insulating film 17 is formed on the entire surface.
．． 18 is formed, and predetermined portions of these insulating films 17 and 18 are etched away to form openings 191 to 194.
Next, for example, an aluminum film is formed on the entire surface by sputtering, and then this aluminum film is patterned into a predetermined shape by etching to form electrodes 20 to 23, thereby completing the intended linear IC.

As shown in FIG. 14, the linear IC according to the embodiment
The linear I according to Example I shown in FIG. 1 except that the silicon epitaxial layer 42 is p-type and also forms part of the base region.
It has a substantially similar configuration to C.

According to the linear IC of this embodiment (2), in addition to the same effects as those of the embodiment I, there is a first-order effect. That is,
Burying of reverse npn type bipolar transistor Q2 W! Since the emitter region composed of I2 has a higher impurity concentration than the cache region, the efficiency of carrier injection from the emitter region to the base region is high, and therefore the reverse direction npn
hFE of the type bipolar transistor Q2 can be improved. Therefore, a high-performance differential amplifier can be obtained.

The method for manufacturing a linear IC according to this Example ① is as follows: Example I
For example, in the process shown in FIG.
For example, B is added in the silicon epitaxial layer 43 after the formation of
The process is the same as that described in Example I, except that the p-type impurity is selectively implanted using, for example, a photoresist mask to make the p-type impurity p-type.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention. It is.

For example, the present invention can be applied to various semiconductor integrated circuit devices having forward bipolar transistors and reverse bipolar transistors.

〔Effect of the invention〕

The effects obtained by one representative invention among the inventions disclosed in this application will be briefly described.

It is as follows.

That is, it is possible to improve the integration density of transistors.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a linear IC according to Example I of the present invention, and FIG. 2 is a circuit diagram showing a cascode-connected differential amplifier. 3 to 13 are cross-sectional views showing an example of the manufacturing method of the linear IC shown in FIG. 1 in order of steps, and FIG. 14 is a cross-sectional view showing a linear IC according to Example 1 of the present invention. In the figure, 1... semiconductor substrate, 2... buried layer, 4...
... silicon epitaxial layer, 5 ... field insulating film, 6, 7 ... base region, 8 ... emitter region, 9 ... collector region, 13 ... polycrystalline silicon film,
10゜11.14.15.17.18...Insulating film, 2
0 to 23...electrode, Q, to Q4...npn type bipolar transistor. Figure 2 Vtc lol 3 A Figure 1O Figure 11 Figure 1df 1 2 Figure 13

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having a forward bipolar transistor and a reverse bipolar transistor,
A semiconductor integrated circuit device, wherein the forward bipolar transistor and the reverse bipolar transistor are provided in the same cell. 2. The semiconductor integrated circuit device according to claim 1, wherein the forward bipolar transistor and the reverse bipolar transistor are provided with a common buried layer. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the forward bipolar transistor and the reverse bipolar transistor are npn bipolar transistors. 4. Claims 1 to 4, wherein the forward bipolar transistor and the reverse bipolar transistor constitute a cascode-connected differential amplifier.
The semiconductor integrated circuit device according to any one of item 3. 5. The semiconductor integrated circuit device according to any one of claims 1 to 4, wherein the semiconductor integrated circuit device is a linear IC.