JPS6381892A - Method of dividing breakable board for electric circuit - Google Patents

Method of dividing breakable board for electric circuit

Info

Publication number
JPS6381892A
JPS6381892A JP22686986A JP22686986A JPS6381892A JP S6381892 A JPS6381892 A JP S6381892A JP 22686986 A JP22686986 A JP 22686986A JP 22686986 A JP22686986 A JP 22686986A JP S6381892 A JPS6381892 A JP S6381892A
Authority
JP
Japan
Prior art keywords
dividing
board
divided
electric circuit
terminal electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22686986A
Other languages
Japanese (ja)
Inventor
深井 徹也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soshin Electric Co Ltd
Original Assignee
Soshin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soshin Electric Co Ltd filed Critical Soshin Electric Co Ltd
Priority to JP22686986A priority Critical patent/JPS6381892A/en
Publication of JPS6381892A publication Critical patent/JPS6381892A/en
Pending legal-status Critical Current

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  • Details Of Cutting Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明け、電気回路用複数取り基板の分割法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for dividing a multi-layer board for electric circuits.

〔従来の技術〕[Conventional technology]

電気回路用複数取り基板を個々の基板に分割する場合、
従来は、まず分割すべぎ個々のV板端部の両面接続部の
縁辺上にスルーホール及び切断溝を設けておき、次いで
、端子電極及びスルーホール接続を印刷形成し、然る後
に前記切断溝に沿って基板の分割を行なうようにしてい
た。
When dividing a multi-board board for electrical circuits into individual boards,
Conventionally, through-holes and cutting grooves are first provided on the edges of the double-sided connection parts of the ends of each V plate to be divided, and then terminal electrodes and through-hole connections are formed by printing, and then the cutting grooves are formed. The board was divided along the lines.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、このように先に切断溝をつけておいてか
ら、端子電極及びスルーホール接続を印刷形成する場合
には、切ft7i溝にベース]・が流れ込み、分割後、
隣接する端子電極間が短絡し易いという欠点があった。
However, if the terminal electrodes and through-hole connections are formed by printing after forming the cut grooves in this way, the base] will flow into the cut grooves, and after dividing,
There is a drawback that short circuits easily occur between adjacent terminal electrodes.

そこで本発明は、切断1j6にペーストが流れ込むのを
防止し、隣接する端子電極間の短絡を防止した電気回路
用複数取り基板の分割法を促供することを1的とする。
Accordingly, one object of the present invention is to promote a method for dividing a multi-section board for electric circuits that prevents paste from flowing into the cuts 1j6 and prevents short circuits between adjacent terminal electrodes.

(問題点を解決するための手段) 上ン[1的を達成づ−るため、本発明にJ3いては、複
数取り!5板の分割すべき個々の基板端部の両面接続部
の縁辺りにスルーホールを設けておき、端子111極及
びスルーボール1a続を印刷形成した後、レーザースク
ライブ等により切断溝を形成し、該切断11’iに沿っ
て分割することを特徴とするものである。
(Means for solving the problem) [In order to achieve one target, the present invention uses J3 and multiple targets! A through hole is provided around the edge of the double-sided connection part at the end of each board to be divided into five boards, and after printing and forming the terminal 111 pole and through ball 1a connection, cut grooves are formed by laser scribing or the like. It is characterized by dividing along the cut 11'i.

〔作 用〕[For production]

このように、印刷(りに切Igi溝を形成して分割する
ことによって、切断溝へのペーストの流れ込みが防1に
でき、端子電極間の短絡を防ぐことができる。
In this way, by forming and dividing the printing grooves, it is possible to prevent the paste from flowing into the cutting grooves, and to prevent short circuits between the terminal electrodes.

〔実施例〕〔Example〕

以下、本発明方法を用い、電気回路用複数取り基板を分
割する場合の一実施例を図面に基づいて説明する。
EMBODIMENT OF THE INVENTION Hereinafter, one example of dividing a multi-chip board for electric circuits using the method of the present invention will be described based on the drawings.

電気回路用複数取り基板である誘電体基板、例えばアル
ミナ基板1は、厚さ数ミリメートルの平板を長方形状に
形成したもので、まず、第1図に示す如く、分、I、1
1すべき個々の基板端部の両面接続部に相当する部分の
縁辺上であるアルミナ基板1の上半部中央及び下半部中
央に、それぞれ所定間隔をおいて、横方向にスルーホー
ル2を複数穿設づ゛る。
A dielectric substrate, for example, an alumina substrate 1, which is a multi-layer substrate for electric circuits, is a rectangular flat plate with a thickness of several millimeters.
Through holes 2 are laterally formed at a predetermined interval in the center of the upper half and the center of the lower half of the alumina substrate 1, which are on the edges of the parts corresponding to the double-sided connection parts of the ends of the individual boards to be processed. Multiple holes are drilled.

ついで、同様に第1図に示す如く、このスルーホール2
の周りにアルミナ基板1の表尖両側に長方形状に端子電
極3を複数印刷し、それによってスルーホール2も接続
する。尚この際他の構成部品があるin合は同時に印刷
する。
Next, as shown in FIG. 1, this through hole 2
A plurality of terminal electrodes 3 are printed in a rectangular shape on both sides of the top surface of the alumina substrate 1 around the terminal electrodes 1, and the through holes 2 are also connected thereto. At this time, if there are other components, they are printed at the same time.

次に第2図に示す−如く、アルミナ基板1の上半部と下
半部間並びに1−半部中央及び下半部中央のスルーホー
ル2上にそれぞれ横方向にレーザー光等によりスクライ
ブiff 4あるいはミシン目等の切IIJi満を形成
する。
Next, as shown in FIG. 2, a laser beam or the like is used to scribe horizontally between the upper and lower halves of the alumina substrate 1 and on the through holes 2 at the center of the first half and the center of the lower half. Alternatively, form a cut such as a perforation.

イして最後に、第3図に示す如くスクライブ満4等の切
rF+溝に沿って複8!!取りM板Cあるアルミナ基板
1を切断し、個々の基板1a、1b、1c。
Finally, as shown in Fig. 3, scribe the 4th grade rF+groove along the multiple 8! ! Alumina substrate 1 with M plate C is cut into individual substrates 1a, 1b, and 1c.

1dを分割形成する。1d is divided and formed.

以上のように、電極印刷及びスルーホール接続の1りに
、スフライ1溝4等の切断溝を形成し、分υIJ“るこ
とぐ、スクライブ満4等の切断溝にペーストが流れるの
を防止でき、端子電極間の短絡が防げる。
As described above, cutting grooves such as swivel groove 1 and 4 can be formed in one of the electrode printing and through-hole connections, and paste can be prevented from flowing into the cutting grooves such as minute υIJ'' and scribe groove 4. , short circuit between terminal electrodes can be prevented.

尚、上記実施例はり根として、誘電体であるアルミナ基
板1を用いているが、その他の基板でもよく、また、本
発明方法は他の磁性体等の基板の分〃1にも適用できる
Although the dielectric alumina substrate 1 is used as the beam in the above embodiment, other substrates may be used, and the method of the present invention can also be applied to substrates made of other magnetic materials.

〔発明の効果〕〔Effect of the invention〕

本発明は以上のにうに、電気回路用複数取り基板の分割
すべき個々の基板端部の両面接続部の縁辺上にスルーホ
ールを穿設し、端子電極及びスルーホール接続を印刷形
成した後に切断1tを形成して分割するようにしたから
、分割用の切断f+’l’+にペーストが流れ込むこと
はなく、端子電極間の短絡を防止することができる。
As described above, the present invention involves drilling through holes on the edges of the double-sided connection parts of the individual board ends to be divided into multiple circuit boards for electric circuits, printing and forming terminal electrodes and through-hole connections, and then cutting. Since it is divided by forming 1t, the paste will not flow into the dividing cut f+'l'+, and short circuits between the terminal electrodes can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明方法の一実施例を示すものぐ、第1図はアル
ミナ基板にスルーホールを穿設し、かつ端子電極及びス
ルーホール接続を印刷形成した状態を示す平面図、第2
図はさらにスクライブ溝を形成した状態を示す平面図、
第3図は前記スクライブ溝に沿ってアルミナ基板を分割
した状態を示す平面図である。 1・・・アルミナ基板   2・・・スルーホール3・
・・端子電極  4・・・スクライブ溝歳1因    
兼20
The figures show one embodiment of the method of the present invention. Fig. 1 is a plan view showing a state in which through-holes are formed in an alumina substrate and terminal electrodes and through-hole connections are printed.
The figure is a plan view showing a state in which scribe grooves are further formed.
FIG. 3 is a plan view showing a state in which the alumina substrate is divided along the scribe grooves. 1...Alumina substrate 2...Through hole 3.
...Terminal electrode 4...Scribe groove age 1 factor
cum 20

Claims (1)

【特許請求の範囲】[Claims] 1、誘電体、磁性体等の複数取り基板を切断溝に沿って
個々の基板に分割する電気回路用複数取り基板の分割法
において、前記分割すべき個々の基板端部の両面接続部
の縁辺上にスルーホールを穿設し、端子電極及びスルー
ホール接続を印刷形成した後、切断溝を形成し、然る後
複数取り基板を個々の基板に分割することを特徴とする
電気回路用複数取り基板の分割法。
1. In a method for dividing a multi-layer board for electric circuits in which a multi-layer board made of dielectric material, magnetic material, etc. is divided into individual boards along cutting grooves, the edges of the double-sided connection parts of the ends of the individual boards to be separated. A multi-chip board for electrical circuits, characterized in that a through-hole is formed on the top, a terminal electrode and a through-hole connection are formed by printing, a cutting groove is formed, and the multi-cavity board is then divided into individual boards. Substrate division method.
JP22686986A 1986-09-25 1986-09-25 Method of dividing breakable board for electric circuit Pending JPS6381892A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22686986A JPS6381892A (en) 1986-09-25 1986-09-25 Method of dividing breakable board for electric circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22686986A JPS6381892A (en) 1986-09-25 1986-09-25 Method of dividing breakable board for electric circuit

Publications (1)

Publication Number Publication Date
JPS6381892A true JPS6381892A (en) 1988-04-12

Family

ID=16851846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22686986A Pending JPS6381892A (en) 1986-09-25 1986-09-25 Method of dividing breakable board for electric circuit

Country Status (1)

Country Link
JP (1) JPS6381892A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51103262A (en) * 1975-03-07 1976-09-11 Hitachi Ltd SERAMITSUKUPATSUKEEJINOSEIZOHO
JPS51125865A (en) * 1975-04-25 1976-11-02 Hitachi Ltd Method of manufacturing ceramic wiring substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51103262A (en) * 1975-03-07 1976-09-11 Hitachi Ltd SERAMITSUKUPATSUKEEJINOSEIZOHO
JPS51125865A (en) * 1975-04-25 1976-11-02 Hitachi Ltd Method of manufacturing ceramic wiring substrate

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