JPS6380783A - Compensator - Google Patents

Abstract

PURPOSE:To delete the number of memories thereby to prevent a rotating speed from varying due to a variation in a load torque by forming a new control signal whenever a new rotation error occurs, and updating one memory value whenever two or more new rotation errors are obtained. CONSTITUTION:A calculator 5 of a compensator 4 reads out a digital signal (b) of a speed detector 3 to correct it to a speed detection value S. This value S is subtracted from a reference value to calculate the rotating error E of a motor 1. A control signal Y is calculated from the error E and the output value V0 of a memory 6, output to a D/A converter 7, which converts it to a control signal C. In this case, a composite error Eg is formed from a plurality of errors E, and the output value V0 of the memory 6 is updated and stored by using the error Eg.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a compensator used within a feedback control loop.

As an example of conventional technology feedback control, for example, a motor speed control device that detects the rotational speed of a motor using a speed detector and controls the power supplied to the motor based on the detection signal is a capstan of a video tape recorder. Although it is widely used in motors, cylinder motors, etc. (see, for example, Japanese Patent Application No. 142,724/1989 proposed by the present applicant), the compensator used in such speed control devices , the traditionally used proportional
Only integral/differential compensation was performed, and it was not possible to sufficiently suppress fluctuations in rotational speed due to fluctuations in load torque.

In order to solve such problems, the applicant has filed a patent application filed in 1983.
In Japanese Patent Application No. 0-229143 and Japanese Patent Application No. 60-229144, a high-performance motor speed control device which uses a compensator of a new configuration and is highly resistant to load torque fluctuations is devised. That is, patent application No. 60-229143
No. 60-229144 discloses a rotation sensor that generates an alternating current signal with a period corresponding to the rotational speed of a motor, a speed detection means that detects multiple times per rotation of the motor based on the alternating current signal of the rotation sensor, The speed control system is controlled by a compensating means which generates a control signal by calculating and storing a gap in the detection signal of the speed detecting means, and a power amplifying means (driving means) which supplies the motor with electric power according to the control signal of the compensating means. It consists of

Furthermore, a rotation error detection means for obtaining a rotation error in response to a detection signal of the speed detection means, a memory means for storing NxL (plural) memory value groups M[0] to M[NxL-1], and a memory. A composite value calculation means (memory output value creation means) that essentially calculates a composite value that is compositely calculated using Nx memory value groups separated by L intervals of the means, and a composite value and rotation of the composite value calculation means. update storage means for substantially sequentially updating and storing the memory value of the memory means with an update value corresponding to a value obtained by calculating and combining the rotation errors of the error detection means; and a combination value of the composite value calculation means and the rotation of the rotation error detection means. A high-performance motor speed control device is realized by using a compensating means (compensator) having a control signal generating means that generates a control signal by calculating and synthesizing errors.

Problems to be solved by the invention However, Japanese Patent Application No. 60-229143 and Patent Application No. 6
In the compensator configuration used in No. 0-229144, it is essential to use a large number of digital memories.
Usually 16bits x 1000words = 16kbi
A memory of about ts is required. Although the price of IC elements for memory is rapidly decreasing due to recent improvements in semiconductor manufacturing technology, using a memory as large as 16 kbits is not preferable because it causes a significant increase in cost.

Taking these points into consideration, the present invention examines a compensator that uses a large amount of memory as shown in the example above, and significantly reduces the number of required memories without deteriorating control performance. It is.

Means for Solving the Problems The present invention includes error detection means that obtains a digital error at every predetermined timing or approximately every predetermined timing, and a composite error that generates a composite error by combining a plurality of digital errors of the error detection means. generating means, and the composite error generating means substantially sequentially converting one of the plurality of memory values each time the error detecting means obtains Q new digital errors (here, Q is an integer of 2 or more). update storage means for updating and storing an updated value corresponding to the value obtained by calculating and combining the synthetic error and at least one of the memory values; and each time the error detecting means obtains a new digital error, the digital error and at least one The above-mentioned problem is solved by providing a control signal generating means for generating a control signal by calculating and synthesizing the memory values.

Operation In the present invention, by adopting the above configuration, a high-performance compensator is expressed with a small number of memories (1/Q). Even in a motor speed control device using an i-compensator, as shown in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, the influence of fluctuations in a specific frequency of load torque can be significantly reduced. I was able to do that. In other words, the compensator of the present invention provides high-performance control '4B.
The device can be constructed economically.

Embodiment Hereinafter, a compensator according to an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an example of a motor speed control device using the compensator of the present invention. In FIG. 2, a DC motor 1 directly rotationally drives a rotation sensor 2 and a load 10. In FIG. The rotation sensor 2 rotates 24 times per rotation as the motor 1 rotates (Zq is an integer of 2 or more, and in a capstan motor of a video tape recorder, usually
Zero rotation sensor 2 that generates an AC signal a of Zq=357)
The alternating current signal a is input to the speed detector 3, and a digital signal corresponding to the period of the alternating current signal a is obtained.

A specific example of the configuration of the speed detector 3 is shown in FIG.

The AC signal a is waveform-shaped by a waveform shaping circuit 31,
A shaped signal g is obtained. The shaped signal g is input to an AND circuit 33 and a flip-flop 35. AND circuit 3
The clock pulse p of the oscillation circuit 32 and the overflow output signal W of the counter 34 are also input to the input side of the 0 oscillation circuit 32, which is composed of a crystal oscillator, a frequency divider, etc., and is configured to adjust the frequency of the shaped signal g. The clock pulse p (approximately 500 kHz) is generated at a considerably higher frequency. The counter 34 is a 12-bit AF counter that counts up its contents every time the output pulse h of the AND circuit 33 arrives. Further, the overflow output signal W is "H" when the counter content of the counter 34 is less than a predetermined value, and when the count content of the counter 34 becomes more than a predetermined value, W changes to "L" (here, 'H' represents a high potential state, and "L" represents a low potential state).

The data input type flip-flop 35 uses the falling edge of the shaping signal g as a trigger signal to take in "H" input to the data input terminal, and sets its output Q to "H"(q-"H'). , reset signal r from compensator 4
When becomes I('', counter 34 and flip-flop 3
The internal state of 5 is reset (b-”LLLLLLLL
LLLLL″, W-I (ゝ, q=″″L′″).

Next, the operation of the speed detector 3 shown in FIG. 3 will be explained.

It is now assumed that the counter 34 and the flip-flop 35 have been reset by the reset signal r. When the output signal g of the waveform shaping circuit 31 changes from ``L'' to ``H'', the clock pulse p of the oscillation circuit 32 is output as the output signal of the AND circuit 33.The counter 34 counts the output signal. Its internal state is changed. When the output signal g of the waveform shaping circuit 31 changes from "H" to L, the output signal g of the AND circuit 33 becomes "L", and the counter 34 maintains its internal state. do.

Further, the flip-flop 35 takes in data "H" at the falling edge of the signal g, and changes its output signal q from "L" to "H". The digital signal S of the counter 34 has a value proportional to the cycle length of the alternating current signal a of the rotation sensor 2, and is inversely proportional to the rotation speed of the motor 1. A compensator 4, which will be described later, looks at the output signal q of the flip-flop 35, and when q becomes "H", inputs the digital signal of the counter 34, and then sets the reset signal r to "H" for a predetermined short period of time. The counter 34 and flip-flop 35 are reset to their initial states in preparation for the next speed detection operation. Note that when the rotational speed of the motor l is too slow, the internal state of the counter 34 exceeds a predetermined value because the period of the output signal g of the waveform shaping circuit 31 is long, and the overflow output signal W changes from "H" to "L". Instead, the output signal of the AND circuit 33 becomes L6, and the counter 34 may hold a predetermined large value.

The compensator 4 in FIG. 2 is composed of an arithmetic unit 5, a memory 6, and a D/A converter 7, and calculates and processes the digital signal of the speed detector 3 using a built-in program, which will be described later, and outputs a control signal C. do. The control signal C of the compensator 4 is input to the power amplifier 8 (drive means), and the power amplified drive signal d
(a current proportional to the control signal C) is supplied to the motor 1. Therefore, a speed control system is constituted by the motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 (driving means), and the rotation speed of the motor 1 is controlled to a predetermined value.

The memory 6 of the compensator 4 is divided into a ROM area (ROM: read-on 11-memory) in which predetermined programs and constants are stored, and a RAM area (RAM: random access memory) in which necessary values are stored. The arithmetic unit 5 performs predetermined operations and calculations according to a program in the ROM area. FIG. 1 shows a specific example of the program. Next, the operation will be explained in detail.

(1) <Error detection means IA> First, the arithmetic unit 5 uses the flip-flop 35 of the speed detector 3.
is inputting the output signal q of
It detects the period and monitors the output of a new digital signal. When q becomes "H", the digital signal of the speed detector 3 is read, and it is changed to the speed detection value S (digital value) corresponding to the digital signal b, and the reset signal is set to "H" for a predetermined period of time to increase the speed. Counter 3 of detector 3
4 and reset the flip-flop 35. Subtract the speed detection value S from the predetermined reference value 5ref and multiply that value by R times (
Here, R is a predetermined positive constant), and the current rotational error E (digital error) of the motor 1 is calculated [E-R・
(Srer-3)], that is, a new digital error E is obtained at every predetermined timing (every time the speed detector 3 outputs a new digital signal) or approximately every predetermined timing.

(2) <Control signal generation means IB> The memory output value ■0 to be described later and the current digital error E are set at a predetermined ratio D:1 (here, D is a constant of 0.5≦D≦1, preferably D -1) to calculate the control signal value Y (Y=E+D-VO), output the control signal value Y to the D/A converter 7, and output the DC voltage corresponding to the value of Y ( control signal).

(3) <Digital error time series storage IC> Store and save the current new digital error E in the memory value F [fl] corresponding to the first count variable 11 described later (F
[+ 1] = E).

(4) <First counting means ID> With Q (here, Q is an integer of 2 or more) as the mad (modulum), count up the first count variable 11 every time a new digital error E is obtained. , i.e. +1-11
After setting it to +1 (make 11+1 a new If),
If it is It-Q, reset 11 to O. If such an operation is performed, I1 will be an integer between 0 and Q-1. Note that the initial value of 11 is 0. If 11 is 0, then (5
) and subsequent operations are executed, and if I1 is not O, the operation returns to (1).

(5) <Synthetic error creation means IE> By the above-mentioned digital error time series storage operation, F[m
](m-0, 1, . . . +, Q-1) stores Q consecutive digital errors. Among these, Fd (
Here, Fd is an integer greater than or equal to 2 and less than or equal to Q).
Fd) and a predetermined ratio Bm (m=1.2.
....

Fd) is added and synthesized to create a synthesis error Eg. That is, Fd Eg=Σ Bm −F [Q−m] ・−・・+
l]m=1 Here, the coefficient Bm is Bm=BFd-m+1 (m=1.2....,Fd
) −−+2) There is a relationship. Furthermore, Fd Σ Bm=1 (
3) Standardized to m・1.

(6) <Second counting means IF> Nx-L (Generally, Nx is an integer greater than or equal to 1, and L is an integer greater than or equal to 4. However, when Nx is an integer greater than or equal to 2, and L is (Zq/Q)
Since it is preferable that the value is an integer multiple of , such a case will be described below. ) as mod,
Every time the first count variable 1 becomes 0 (every time Q new digital errors E are obtained), the second count variable 12 is counted and amplified. That is, after making it +2-12+1,! If 2=NxL, reset I2 to O.

If such calculation is performed, I2 will be from 0 to NxL-1
be an integer between . Note that the initial value of I2 is NxL-1.

(7) <Memory output value creation means IG> Integer J equal to 12 (J=+2), L in the ram area
A group of Nx memory values M [J−nL (
mod NxL)] (n=1°..., Nx) to create the memory output value ■0 using the following equation.

n=1 Here, the value of the ratio Wn is 0<Wn<2/Nx (n=1. ..., Nx)
−(51, and is further standardized as n=1. Specifically, when Nx≧2, Wn=1/N x (n-1,...+, Nx)
......(71), the formula (4) becomes the memory value group M[J-nL(nod NxL)] (n=1.
...+, Nx) are simply added and combined and then divided by Nx (an integer), which requires a very large number of calculations, M, iB.

(8) <Update storage means IH> Memory output value ■ Calculate the update value by calculating and combining 0 and the synthesis error Eg at a ratio of 1:1, and store the memory in the RAM area corresponding to the second count variable I2. The value M [12] is updated (M [+ 21 = Eg 0) and stored until the next update. Thereafter, the operation returns to fi+.

The fact that the motor speed control device using the compensator of the present invention shown in this embodiment is extremely strong against a specific frequency component of the load torque fluctuation caused by the load IO shown in FIG.
Prior patent application (Japanese Patent Application No. 60-229143.6O-229
144). Further, as shown in this embodiment, the control signal generating means IB generates a new control signal every time the error detecting means IA obtains a new digital error, and the error detecting means IA generates Q new digital errors. By making the update storage means 11 update one memory value each time the update storage means 11 (required memory number) can be reduced to 1/Q by the update storage means IH. Even if the number of memories was significantly reduced in this way, we were able to maintain the effect of increasing the strength of load torque fluctuations against specific frequency components (effects that do not cause rotational speed fluctuations). It can be seen that when the value of L is increased, the frequency component improved by the above-mentioned compensator becomes considerably lower than the detection frequency of the speed detector. By using Eg to update and save the memory values, the update frequency of the update storage means IH can be reduced to 1/Q (even if it is possible to do so without causing a negative effect on the stability of the control system and the above-mentioned improvement effect). This is due to the fact that

Furthermore, as shown in this embodiment, a composite error Eg is obtained by combining Fd consecutive digital errors, and a composite error Eg is obtained by combining Fd consecutive digital errors.
g and memory output value■. The memory value M [
12], it was also found that it is possible to prevent the operation of the feedback control system from becoming unstable due to unnecessary noise components included in the digital error signal. This has the effect of preventing the influence of fairly high-frequency fluctuations included in the digital error E from entering the memory value of the update storage means IH or the memory output value of the memory output value creation means IG, by the synthetic error creation means IB. This is because I was able to obtain .

In addition, in the case of a motor speed control device using the compensator of the present invention, the above-mentioned value of L is set as L= (Zq/Q) ・
If k (here, k is an integer greater than or equal to 1), there is an effect of greatly suppressing rotational speed fluctuations due to load torque fluctuations with a period twice (an integral multiple) of one rotation period of the motor 1. Such an effect is highly desirable in the case of video tape recorder capstan motors. This will be explained. Since the load of the capstan motor is a magnetic tape or a pinch roller, the load fluctuation generated by the load 10 is a component that is synchronized with the rotation of the motor 1 (periodic load fluctuation with one revolution of the motor 1 as the basic cycle). In addition, load fluctuation components with a frequency lower than the rotational frequency of the motor 1 often occur. Such load fluctuations cause fluctuations in the rotational speed of the capstan motor, causing wow and flutter in the tape speed. By the way, it has been found that such load fluctuations are often periodic fluctuations having a period that is an integral multiple of the period of one revolution of the motor 1. Therefore, due to the above-mentioned effects, it is possible to effectively reduce considerably low-frequency fluctuations in the rotational speed of the motor 1 due to load torque fluctuations.

FIG. 4 shows an example of a program for the compensator 4 of the present invention, which takes into consideration the stability of the entire control system. Here, we have improved the method of calculating update values in the update storage means, the number of memory output values prepared in the memory output value creation means, and the way of using memory output values of the memory output value creation means in the control signal creation means. are doing. Next, its operation will be explained in detail (the overall configuration of the motor speed control device is the same as that shown in FIG. 2, and the explanation will be omitted).

0υ error detection means 4A> First, the arithmetic unit 5 detects the
It inputs the output signal q of , and waits for the signal q to become "H". In other words, the speed detector 3 detects (half) the AC signal a.
It detects the period and monitors the output of a new digital signal. When q becomes 'H', the digital signal of the speed detector 3 is read and the speed detection value S (digital value) corresponding to the digital signal is changed, and the reset signal r is set to 'H' for a predetermined period of time to increase the speed. Counter 3 of detector 3
4 and reset the flip-flop 35. Subtract the speed detection value S from the predetermined reference value 5ref and multiply that value by R times (
Here, R is a predetermined positive constant), and the current rotational error E (digital error) of the motor 1 is calculated [F, = R・
(Sref-3)3. That is, at every predetermined timing,
Alternatively, a new digital error E is obtained approximately every predetermined timing.

Control signal generation means 4B> A memory output value vO, which will be described later, and a current digital error E are calculated and combined at a predetermined ratio D:1 to calculate a control signal value Y (Y-E+D-VO).

The control signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y.

α1 <Save digital error time series 4C> Store and save the current new digital error E in the memory value F[11] corresponding to the first count variable ■1 described later (F
[11l-E).

[First counting means 4D] With Q as mod, the first force, the runt variable ■1, is counted up each time a new digital error E is obtained (.11 is Qa (here, Qa is (an integer smaller than Q), the memory output value ■0 is set to V[Px
(1) If 1 is not equal to Qa, such a changing operation is not performed. As a result, in the range II < Qa, VQ-V [PX-11 (described later), and 11≧Q
In the range a, V O=V [P x]. Further, if (1) is 0, the operation after α is executed, and if 11 is not 0, the operation returns to Oυ.

α9 <Synthetic error creation means 4B> F [m
Q consecutive digital errors are stored in l (m=0.1.-.+, Q-1). F in this
d latest digital errors F(Q-mko (m=1.2
．． ..., Fd) at a predetermined ratio Bm (m
=1.2. ....

Fd) is added and synthesized to create a synthesis error Eg [[11, +21. (Type 31).

aS <Second counting means 4F> With Nx-L as mod, the first count variable ■
Every time 1 becomes 0 (every time Q new digital errors E are obtained), the second count variable 12 is counted up.

07+ <Memory output value creation means 4G> After sequentially transferring the contents of the register variable v[m+1] to V[ml (m=o, 1. . . .).

Calculate the integer J by adding Px (here, Px is an integer greater than or equal to 1 and less than or equal to 3, and Px = 1 is preferable) to the second count variable ■2 with NxL as mod [
J-12+Px (mod NxL)]. Memory value group M in RAM area [J-nL (mod NxL)]
Enter the latest memory output value calculated by the following formula using (n=1°..., Nx) into V[Pxl.

Nx Here, the value of Wn is +51. (61 formula and (7) formula are satisfied. In other words, from V[Pxl to V[01
A group of Px+1 consecutive memory output values is obtained.

At this time, if the integer J in formula (8) when calculating V[Pxl is Jl, and the integer J in formula (8) when calculating ■[0] is J2, then the relationship of Jl - J2 + Px There is.

Next, the memory output value VO used first in the control signal generation means is set to VIPX-1] (VO=V [P
x-13>.

α 〫〈Update storage means 4H〉 After transferring the contents of register variable X[m+1] to
1), X [2Kd] (here, Kd is an integer, and Kd = 3 is preferable) with the old memory output value V[0] created by the memory output value creation means and the synthesis error Eg
Input the composite value calculated and synthesized at the ratio of tit (X [2Kd = Eg + V [0)]. That is, X
Obtain 2)(d+1 added values (added value of memory output value and synthesis error) consecutive to X[0] from [2Kd].Nx
Second count variable with L as mod Calculate the integer K by subtracting Kd from 2 [K-12-Kd (mod N
xL)],, then a predetermined positive ratio Cm(
m=o.

A new updated value is obtained by adding and combining the multiplied values by 1, .

shall be. Here, the ratio Cm has the following relationship.

CCm=C2Kd-(m=o, 1..., Kd)
-.=Oω After that, the operation returns to αυ.

As in this embodiment, an operation for taking a weighted average may be inserted into the update storage means 4H, or the first memory output value V of the memory output value creation means 4G used in the control signal creation means 4B.
O(V[Pxco)] and the second memory output value v[ of the memory output value creation means 4G used in the update storage means 4H.
It was confirmed that if a predetermined deviation (V[Px] is ahead of V[0]) is provided between V[0], the operation of the entire control system becomes stable.

In particular, the Px and QaO values, which are related to the timing of their use, are deeply related to the number of operands Fd of the composite error creation means 4E, and (
It was also found that it is better to set QPx-Qa)≧(Q+Fd)/2.

This is because the error detection means 4A detects the usage timing in the control signal creation means 4B compared to the usage timing in the update storage means 4H of the same memory output value (for example, V[O]) of the memory output value creation means 4G. When converted into the number of times, it means to be faster by (Q+Fd)/2 or more times.

FIG. 5 shows another example of a program for the compensator 4 of the present invention, which takes into consideration the stability of the entire control system.

Here, improvements have been made in the method of calculating memory output values in the memory output value creation means and the number of memory output values to be prepared, as well as the way in which the memory output values of the memory output value creation means are used in the control signal creation means.

Next, its operation will be explained in detail (the overall configuration of the motor speed control device is the same as that shown in FIG. 2, and the explanation will be omitted).

(21) <Error detection means 5A> First, the arithmetic unit 5 uses the flip-flop 35 of the speed detector 3.
It inputs the output signal q of , and waits for the signal q to become "H". In other words, the speed detector 3 detects (half) the AC signal a.
It detects the period and monitors the output of a new digital signal. When q becomes "H", read the digital signal of the speed detector 3, change it to speed detection 1is (digital value) corresponding to the digital signal, and set the reset signal r to "H" for a predetermined period of time to detect the speed. The counter 34 and flip-flop 35 of the device 3 are reset. EE subtracts the speed detection value S from a predetermined reference value 5ref, multiplies that value by R (here, R is a predetermined positive constant), and calculates the current rotational error E (digital error) of the motor 1. =R・
(Sref-3)]. That is, at every predetermined timing,
Alternatively, a new digital error E is obtained approximately every predetermined timing.

(22) <Control signal generation means 5B> A predetermined ratio D= of the memory output value ■0 to be described later and the current digital error E
1, and calculate the control signal value Y (Y =
E + D・VO).

The control signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y.

(23) <Storage of digital error time series 5C> Memory value F[+11 corresponding to the first count variable 11 described later
Store the current new digital error E in
(F[+11=E).

(24) <First counting means 5D> Q is mod (
(method), the first count variable If is counted and amplified every time a new digital error E is obtained. 11 is Qa
(Here, Qa is an integer smaller than Q), the memory output value VO is changed to V[Pxl, which will be described later, and when 11 is not equal to Qa, such a changing operation is not performed. As a result, in the range 11<Qa, VO−V [P
x-1] (described later), and in the range of 11≧Qa, V
O=V [It has become Px. Further, if 11 is O, the operation after (25) is executed, and if 1 is not O, the operation returns to (21).

(25) <Synthetic error creation means 5E> F [mco (m-0,
1, -, Q-1), Q consecutive digital errors are stored. Among these, Fd latest digital errors F[Q-ml (m-1, 2, . . . , Fd) are each given a predetermined ratio Bm (m=1.2, . . . ).

Fd) is added and synthesized to create a synthesis error Eg [fll, (21, f31 formula]).

(26) <Second counting means 5F> Nx-L is m
od C method), the second count variable I2 is counted up every time the first count variable 11 becomes O (every time Q new digital errors E are obtained).

(27) <Memory output value creation means SC> After sequentially transferring the contents of register variable X [m+1] to X [ml (m-0, 1, 2,...+, 2Kd-1), NxL
Px+Kd to the second count variable I2 with nod
(Px is an integer greater than or equal to 1 and less than or equal to 3, and Kd is an integer greater than or equal to 1) [J-12+Px+Q]
x (mad NxL)] * Nx memory value group M in the RAM area [J-nL (nodNxL)]
(n=1.--., Nx) and enter the calculated value calculated by the following formula into X[2Kd].

Nx X[2Kd]=Σ −n −M [J−nL (
n+od NxL) -...Un・1 Here, the value of Wn is +51. +61 formula and (7) formula are satisfied. That is, from X[2Kdl to X[0
2Kd+1 consecutive calculated values (calculated values obtained from Nx memory values separated by L intervals) are obtained. Next, after sequentially transferring the contents of the register variable V[m+1] to V[ml (m=o, 1. ・--, Px-1)
,
Obtain the latest memory output value by adding and combining the multiplied values by d) and put it in V[Pxl.

m=0 Here, the ratio Cm has the relationship αω, 00.

That is, PX+1 consecutive from V[Pxl to ■[0]
memory output values are obtained. At this time, substantially V[
Let Jl be the integer J in @formula when calculating Pxl, and let J2 be the integer J in formula (2) when practically calculating v[0].
Then, there is a relationship of J1=J2+Px. That is,
There is a gap between V[Pxl and ■[0] corresponding to the integer Px. Next, the memory output value vO is set to ■[Px-1] (VO=V[Px-1]).

(2B) <Update storage means 5H> The old memory output value V[03 created by the memory output value creation means and the synthesis error Eg are calculated at a ratio of 1:1 to calculate the update value, and the second Update the memory value M [12] in the RAM area corresponding to count variable 12 M
[+21=Eg+V [0]), is stored and saved until the next update. After that, the operation returns to (21).

As in this embodiment, a calculation for taking a weighted average and a calculation for preparing a plurality of memory output values are inserted into the memory output value creation means 5G, and the memory output value creation means 5G used in the control signal creation means 5B is 1 memory output value■. (V
[Pxl) and the second memory output value v[0] of the memory output value creation means 5G used in the update storage means 5H.
If a predetermined deviation is provided between them (V[Pxl is ahead of V[01]), the operation of the entire control system will be stabilized. In this case as well, (QPx-Qa)≧(Q+Fd)/2
It is better to

It should be noted that calculations using the ratios Wn and Cm are not limited to the above-mentioned forms, and may be any form that substantially realizes the content of the above-mentioned program, and it goes without saying that various equirestricted transformations are possible. stomach.

Also, when a new digital error is obtained, the control signal generating means first performs an operation to output a new control signal,
After that, if the memory output value creation means calculates the memory output value to be used at the next sampling point (timing), the calculation time of the memory output value creation means can be lengthened, and the time required to output the control signal can be increased. Since the time delay can be shortened, it is easy to ensure the stability of the control system.

In each of the above-described embodiments, the compensator is configured by a software program, but the present invention is not limited to such a case. It may be possible to perform the same operation as the one described above.

In addition, various modifications can be made without changing the gist of the present invention.

Effects of the Invention The compensator of the present invention is capable of obtaining extremely good control characteristics at a specific frequency while using a small amount of memory. Therefore, if the compensator of the present invention is used in a feedback loop to configure a control device,
A control device with extremely high performance control characteristics can be obtained at low cost.

For example, when used in a motor speed control device for a capsun motor of a video tape recorder, a high performance motor speed control device can be constructed economically.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an example of a built-in program of the compensator of the present invention shown in FIG. 2, and FIG. 2 is a block diagram showing an example of the configuration of a motor speed control device B using the compensator of the present invention. FIG. 3 is a block diagram showing a specific example of the configuration of the speed detector shown in FIG. 2, FIG. 4 is a flowchart showing another example of the built-in program of the compensator of the present invention, and FIG. FIG. 7 is a flowchart showing another example of the built-in program of the compensator. 1... Motor, 2... Rotation sensor, 3
... Speed detector, 4... Compensator, 5.
...Arithmetic unit, 6...Memory, 7...
...D/A converter, 8...Power amplifier, 10.
... Load, IA, 4A, 5A ... Error detection means, IB, 4B, 5B ... Control signal creation means, IE, 4E, 5E ... Synthesis error creation means;
IG. 4G, 5G...Memory output value creation means, IH. 4H, 5H... Update storage means.

Claims (1)

[Claims] an error detection means for obtaining a digital error at every predetermined timing or approximately every predetermined timing; a composite error creation means for creating a composite error by combining a plurality of digital errors of the error detection means; (where Q is an integer of 2 or more), one of the plurality of memory values is substantially sequentially combined with the composite error of the composite error generating means and at least one of the memory values. update storage means for updating and storing an updated value corresponding to the calculated and combined value; and each time the error detection means obtains a new digital error, the digital error and at least one of the memory values are calculated and combined to generate a control signal. A compensator comprising control signal generating means.