JPS62233089A - Controller for capstan motor - Google Patents

Abstract

PURPOSE:To reduce the fluctuation of the rotating speed on a large scale caused by the fluctuation of the tension of a reel, by providing a memory storage to store rotation errors in a compensatory means. CONSTITUTION:A signal (a) of a rotation sensor 2 is turned into a detection signal (b) by a speed detector 3, which is then turned into a control signal (c) by a compensator 4 to drive a reel motor 1 through a power amplifier 8. A compensator 4 is provided with a computing element 5, a memory storage 6 and a D/A converter 7. A computing element 5 is provided with a rotation error detecting means to find a rotation error, a memory output producing means, a memory updating and storing means to update the memory storage in accordance with the rotation errors and memory output values, a control signal producing means to produce control signals in accordance with the rotation errors and the memory output values, and a reel cycle responding means to increase or decrease the number of memory values treated by the memory updating and storing means and the memory output producing means in accordance with the rotating cycle of the reel. Every time when the speed detector 3 obtains a new detection signal (b), a control signal productive means produces a new control signal. Every time when Q-many detection signals (b) are obtained, the updating and storing means updates one memory.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a control device for a capstan motor.

2. Description of the Related Art A capstan motor control device that detects the rotational speed of a capstan motor using a speed detector and controls the power supplied to the capstan motor based on the detection signal is used in a magnetic tape running device such as a video tape recorder. (For example, the patent application proposed by the applicant in 1982)
However, such control devices only perform proportional, integral, and differential control, which have been used in the past, and do not sufficiently compensate for fluctuations in rotational speed caused by fluctuations in load torque. could not be suppressed.

In order to solve such problems, the applicant has filed a patent application filed in 1983.
In Japanese Patent Application No. 0-229143 and Japanese Patent Application No. 60-229144, we proposed a high-performance motor speed control device that is highly resistant to load torque fluctuations. In other words, the patent application 1986-
No. 229143 and Japanese Patent Application No. 60-229144 disclose a rotation sensor that generates an AC signal with a period corresponding to the rotation speed of a motor, and a speed detection means that performs detection multiple times per rotation of the motor based on the AC signal of the rotation sensor. , a compensating means that calculates and stores a control signal based on the detection signal of the speed detecting means, and a power amplifying means (driving means) that supplies the motor with electric power according to the control signal of the compensating means. It constitutes the #1m system.

Furthermore, a rotation error detection means for obtaining a rotation error in response to a detection signal of the speed detection means, and a memory means for storing Nx1 (plural) memory value groups M[0] to M[N L-1]. , a composite value calculation means (memory output value creation means) that substantially calculates a composite value that is compositely calculated using Nx memory value groups spaced apart by L intervals of the memory means, and a composite value of the composite value calculation means. update storage means for substantially sequentially updating and storing the memory value of the memory means with an update value corresponding to a value obtained by calculating and combining the rotation error of the rotation error detection means; and the composite value and rotation error detection of the composite value calculation means. A high-performance motor speed control device is realized by using a compensating means having a control signal generating means for generating a control signal by calculating and synthesizing rotational errors of the means.

Problems to be solved by the invention Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-22914
It has been found that when the motor speed control device shown in No. 4 is used as a capstan motor control device, it is necessary to make some improvements. For example, it has been found that the capstan motor of a video tape recorder is greatly affected by fluctuations in tensile strength from the take-up reel (or supply reel), causing rotational speed fluctuations. Furthermore, the frequency of tension fluctuations from the reel changes with its winding diameter. Therefore, the special application 1986-
With the configurations of No. 229143 and Japanese Patent Application No. 60-229144, it was not possible to reduce the fluctuations in rotational speed due to the influence of these tensile range fluctuations.

Furthermore, Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-2
In the configuration of No. 29144, it is essential to use a large amount of digital memory, typically 16 bits
A memory of about 100 words=16 kbits is required. Although the price of IC elements for memory is rapidly decreasing due to improvements in semiconductor manufacturing technology in recent years,
Using as much as kbits of memory is undesirable because it causes a significant increase in cost.

The present invention takes these points into consideration and provides a capstan motor control device that sufficiently reduces the influence of tensile run fluctuations from the reel and also reduces the number of required memories.

Means for Solving the Problems The present invention includes a rotation sensor that generates an alternating current signal with a period corresponding to the rotational speed of the capstan motor, and a plurality of detections per rotation of the capstan motor based on the alternating current signal of the rotation sensor. a speed detection means for performing the above, and a compensation means for generating a control signal based on the detection signal of the speed detection means;
The compensation means includes a drive means for driving the capstan motor according to a control signal of the compensation means, and the compensation means includes a rotation error detection means for obtaining a rotation error in response to a detection signal of the speed detection means, and four or more rotation error detection means. memory means for storing memory values of at least one memory value stored in said memory means;
memory output value creation means for creating a memory output value using the memory output values; and an update value corresponding to a value obtained by calculating and combining the memory output value of the memory output value creation means and the rotation error of the rotation error detection means. update storage means for substantially sequentially updating and storing memory values in the memory means; and control for generating the control signal by calculating and combining the memory output value of the memory output value creation means and the rotation error of the rotation error detection means. It has a signal generation means and a reel cycle response means for increasing or decreasing the number of memory values handled by the update storage means and the memory output value generation means according to the rotation cycle of the reel, and the speed detection means obtains a new detection signal. Each time, the control signal generating means generates a new control signal, and each time the speed detecting means obtains Q new detection signals (here, Q is an integer of 2 or more), the updating storage means substantially generates a new control signal. The above problem is solved by configuring one memory value to be updated.

Operation According to the present invention, with the above-described configuration, a high-performance capstan motor control device is realized with a small number of memories. That is, as shown in Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, improvements in the control characteristics of the motor speed control device are designed to always correspond to the frequency of tensile run fluctuations from the detection reel. ,
Moreover, the amount of memory required is also reduced.

Embodiment FIG. 2 shows a basic configuration diagram of a tape running system of a video tape recorder. A magnetic tape 10 fed out from a supply reel Ilb is wound around a cylinder motor 21 by more than 180 degrees by impedance rollers 22 and 23. Video information is recorded on and reproduced from a magnetic tape by a rotating magnetic head mounted on a cylinder motor 21. The magnetic tape 10 is pressed against the capstan motor 1 by a pinch roller 24, runs at a predetermined speed proportional to the rotational speed of the capstan motor 1, and is moved onto the take-up reel l.
It is wound around la.

The rotational speed of the capstan motor 1 fluctuates due to tension fluctuations in the magnetic tape 10 caused by the take-up reel lla and the supply reel llb, causing fluctuations in the magnetic tape running speed (wow, etc.).
flutter) was occurring.

Since the frequency of tension fluctuation is proportional to the rotational speed of the reel, it changes depending on the amount of winding of the magnetic tape 10 on each reel, and occurs over a fairly wide frequency range from the beginning of tape winding to the end of winding. do. In particular, the take-up reel
Due to the influence of la, the rotational speed of the capstan motor l tends to fluctuate greatly.

FIG. 3 shows a configuration diagram representing an embodiment of the present invention.

In FIG. 3, the rotation sensor 2 is connected to the capstan motor 1.
As the motor rotates, an alternating current signal a is generated ZQ times per revolution (Zq is an integer of 2 or more; in a capstan motor of a video tape recorder, it is usually ZQ-357). The alternating current signal a of the rotation sensor 2 is input to the speed detector 3, and a digital signal corresponding to the period of the alternating current signal a is obtained.

A specific example of the configuration of the speed detector 3 is shown in FIG.

The AC signal a is waveform-shaped by a waveform shaping circuit 31,
A shaped signal g is obtained. The shaped signal g is directly input to the AND circuit 33 and the first differentiation circuit 36, and is also input to the second differentiation circuit 38 via the inverter circuit 37. The first differentiation circuit 36 generates a minute width differentiation pulse i at the rising edge of the shaping signal g, and this pulse resets the internal state of the counter circuit 34. The second differentiating circuit 38 generates a differential pulse k of minute width at the falling edge of the shaped signal g, and the second differentiating circuit 38
Load the digital signal j into the latch circuit 39 (input,
data input type flip-flop 4
Set the output to 0.

The clock pulse p of the oscillation circuit 32 and the overflow output signal W of the counter circuit 34 are also input to the input side of the AND circuit 33 . The oscillation circuit 32 is composed of a crystal oscillator, a frequency divider, etc., and generates a clock pulse p (500'kHz) which has a considerably higher frequency than the frequency of the shaped signal g.
degree) has occurred. The counter circuit 34 is a 12-bit up counter that counts up the contents every time the output pulse h of the AND circuit 33 arrives. Further, the overflow output signal W is "H" when the count content of the counter circuit 34 is less than a predetermined value, and when the counter content of the counter circuit 34 is greater than the predetermined value, W is "L".
” (here, “H’ represents a high potential state, and “
("L" indicates a low potential state).The data input type flip-flop 40 takes in "H" input to the data input terminal at the falling edge of the shaping signal g, and changes its output Q to "H". (q=“H”).Furthermore, when the reset signal r from the compensator 4 becomes “H”, the internal state of the flip-flop 40 is reset (q−“L”).
”).

Next, the operation of the speed detector 3 shown in FIG. 4 will be explained.

It is now assumed that the flip-flop 4o has been reset by the reset signal r.

When the output signal g of the waveform shaping circuit 31 changes from "L" to "H", the first differentiation circuit 36 first generates a differentiation pulse i and resets the counter circuit 34. Then, the output signal of the AND circuit 33 The clock pulse q of the oscillation circuit 32 is output as a signal, and the counter circuit 34 counts the output signal and changes its internal state.Next, the output signal g of the waveform shaping circuit 31 becomes "H". ” to “L”, the output signal of the AND circuit 33 becomes “L”, and the counter circuit 34 maintains its internal state.
The second differentiation circuit 38 outputs a differentiation pulse k, loads the state signal j of the counter circuit 34 into the launch circuit 39, and changes the output signal q of the flip-flop 40 from "L" to "H". Therefore, the digital signal S of the launch circuit 39 has a value proportional to the (half) cycle length of the AC signal a of the rotation sensor 2, and is inversely proportional to the rotation speed of the capstan motor l. The compensator 4, which will be described later, is a flip-flop 40.
When q becomes "1", input the digital signal of the launch circuit 39, and then set the reset signal r to "H" for a predetermined short time to initialize the flip-flop 40. Reset to state. Note that when the rotational speed of the capstan motor 1 is too slow, the internal state of the counter circuit 34 exceeds a predetermined value because the period of the output signal g of the waveform shaping circuit 3I is long, and the overflow output signal W
may change from "H" to "L", the output signal of the AND circuit 33 becomes "L", and the counter circuit 34 holds a predetermined large value.

The reel rotation sensor 12 in FIG.
AC signal e in response to the rotation of If (reel or supply reel)
occurs. The reel rotation detector 13 obtains a digital signal 1 proportional to the period of the alternating current signal e. Its specific configuration example is the same as that of the speed detector 3 shown in FIG.
Flip-flop 40 is eliminated).

The compensator 4 in FIG. 3 is composed of an arithmetic unit 5, a memory 6, and a D/A converter 7, and manually inputs the digital signal from the speed detector 3 and the digital signal l from the reel rotation detector 13. , and outputs a control signal C through calculation processing using a built-in program to be described later.

The control signal C of the compensator 4 is input to a power amplifier 8 (driving means), and the power amplified drive signal d (current proportional to the control signal C) is supplied to the capstan motor l.

Therefore, a speed control system is constituted by the capstan motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8 (driving means), and the rotation speed of the capstan motor 1 is controlled to a predetermined value. .

The memory 6 of the compensator 4 is a ROM 81Mi (RoM: read-only memory) in which predetermined programs and constants are stored.
It is divided into a RAM area (CRAM: random access memory) that stores values that are needed at any time. The arithmetic unit 5 performs predetermined operations and calculations according to a program in the ROM area.

FIG. 1 shows a specific flowchart of the program. Next, the operation will be explained in detail.

(l) <Rotation error detection means> First, the arithmetic unit 5 uses the flip-flop 40 of the speed detector 3.
inputs the output signal q of the AC signal a and waits for the signal q to become H''.In other words, the speed detector 3 detects the (half) period of the AC signal a and monitors the output of a new digital signal. When q becomes "Ho", the digital signal S of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal S is changed, and the reset signal r is set to "H" for a predetermined period of time. to reset the flip-flop 4o of the speed detector 3. Predetermined reference value 5
Subtract the speed value S from ref and multiply that value by R (here,
R is a predetermined positive constant), and the current rotational error E of the capstan motor 1 is calculated.

[E=R・(Sref -3)] (2) <Control signal generation means> Memory output value ■ by memory output value creation means described later.

and the current rotation error E to a predetermined ratio D:1 (here,
D is a constant O<D51, preferably D=1), and the control signal value Y is calculated (Y=E+D −V
o) The control signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y.

(3) <First counting means> Using Q (here, Q is an integer of 2 or more) as mod, the first count variable ■ is counted up every time a new speed detection value S is obtained. go.

That is, T1-1. +1 ([1+1 new T1
), then reset T1 to O if I,=Q. If we perform such an operation, r will be from 0 to Q
It will be an integer between -1.

In addition,! The initial value of , is 0. ! If , is 0, +41
．． (51, +61. Execute the operation of +71, and if T1 is not 0, return to the operation of [1].

(4) <Second counting means> Nx-L (Generally, Nx is an integer, and L is an integer of 4 or more. However, it is preferable that Nx is an integer of 2 or more, so
Such a case will be explained below. ) to sod (
modulus), each time the first count variable ■1 becomes O (
The second count variable 12 is counted and amplified every time Q new speed detection values S are obtained. In other words, ■2=I
After making 2+1, if l2=NxL, reset I2 to O. If such an operation is performed, I2 will be an integer between O and NxL-1. Note that the initial value of I2 is N
xL-1, and the initial value of L is a predetermined large integer.

Further, the value of L is changed at any time by a reel cycle responsive means, which will be described later.

(5) <Memory output value creation means> Integer J equal to I2 (J=I2), L in the ram area
A group of Nx memory values M[J-nL(Il
odNxL)] (n-1,...

NK) to create a memory output value v0 using the following equation.

Nx (1) Here, the value of the ratio Wn is 0 < Wn < 2/Nx (n = 1, ・=
..., Nx) ... (2), and furthermore, ΣWn=1 ...
It is standardized as (3). Specifically, Nx≧
2, Wn -1/Nx (n = 1, =...,
Nx )...(4) Then, the formula I1] becomes the memory value group M[J-nL(+wo
d NxL)] (n-1, .--=, Nx) are simply added and combined and then divided by Nx (an integer), making the calculation very simple.

(6) <Update storage means> Calculate an update value by calculating and combining the memory output value v0 and rotation error E by the memory output value creation means at a ratio of 1:1,
The memory value M[I2] in the RAM area corresponding to the second count variable 12 is updated M[12]-E+V. ), stored until the next update.

(7) <Reel cycle response means> Inputs the digital signal l of the reel rotation detector 13 and calculates the reel rotation detection value Ld (digital value) corresponding to the signal 1.
get. Here, Ld is the 6th order which is proportional to the rotation period of the reel, and the value of the basic memory length described above is changed to the reel rotation detection value Ld. After that, the operation returns to (1).

With this configuration, the rotational speed of the capstan motor 1 hardly changes with respect to the tension fluctuation that occurs on the detection reel 1] (the take-up reel lla or the supply reel 1]b). This is because the basic memory length is changed at any time to a value proportional to the rotation period of the detection reel by the reel cycle response means, and the number of memories NxL handled by the update storage means and memory output value creation means changes, resulting in improved control characteristics. This is because the frequency that appears can always be matched to the frequency that corresponds to the rotation period of the detection reel (
For the improvement effect on control characteristics, please refer to the previous IJI patent)
. That is, regardless of the winding diameter of the detection reel 1, it is possible to always improve the control characteristics (disturbance suppression characteristics) of the capstan motor at the frequency of the tension fluctuation of the detection reel 1. Therefore, even if the detection reel 1 causes a large tension fluctuation, the rotational speed of the capstan motor 1 will not fluctuate. Note that since the capstan motor 1 was greatly affected by the tension fluctuation of the take-up reel lla, it is preferable to select the take-up reel lla as the detection reel 1].

Furthermore, as shown in this embodiment, the control signal generating means generates a new control signal every time the speed detector obtains a new detection signal, and updates the control signal every time the speed detector obtains Q new detection signals. If the storage means updates one memory value, the number of memories required for the memory means is substantially reduced by a factor of Q. Even if the number of memories is reduced in this way, the effect of being extremely strong against tension fluctuations of the detection reel (the effect of not causing rotational speed fluctuations) is maintained. This can be explained as follows. It has been found that the frequency component (frequency of tension fluctuation) that needs to be improved by the operation of the memory means, memory output value creation means, and update storage means is considerably lower than the detection frequency of the speed detector. Therefore, even if the frequency of the detection signal of the speed detector used in the update storage means is reduced to 1/Q, the above-mentioned improvement effect can be prevented from being adversely affected.

FIG. 5 shows a flowchart of a program for the compensator 4 that takes into account the stability of the entire control system. Here, the method of calculating the update value in the update storage means and the method of calculating the memory output value in the memory output value creation means are explained. The number of preparations and the method of using the memory output value of the memory output value creation means in the control signal creation means are improved. Also, 1 of the speed detector 3
The amount of calculation required within the detection period is also reduced. Next, the operation will be explained in detail. (The overall configuration is the same as that in FIG. 3, and the explanation is omitted.) (8) <Rotation error detection means> First, the arithmetic unit 5 is connected to the flip-flop 40 of the speed detector 3.
It inputs the output signal q of , and waits for the signal q to become "H". In other words, the speed detector 3 detects (half) the AC signal a.
It detects the period and monitors the output of a new digital signal. When q becomes "H", the digital signal S of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal S is set, and the reset signal is set to "H" for a predetermined period of time to increase the speed. Reset the flip-flop 40 of the detector 3 to a predetermined reference value 5r.
The speed detection value S is subtracted from ef, the value is multiplied by R (here, R is a predetermined positive constant), and the current rotational error E of the capstan motor I is calculated.

[E=R・(Sref −3)] (9) <Control signal generation means> Memory output value V0 by memory output value generation means described later
and the current rotational error E at a predetermined ratio D:1 to calculate the control signal value Y (Y-E+D-Vo).
The control signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y.

Ol<first counting means> With Q as n+od (modulo), count up the first count variable 1 every time a new speed detection value S is obtained, ■1 is Qa (here, Qa is Q ), the memory output value v0 is set to V[Px
(2) If 1 is not equal to Qa, such a changing operation is not performed. As a result, in the range of 1] < Q a, Vo-V [Px-1] (described later),
! In the range of 1≧Qa, vo −V [Pxl. Further, if II is 0, the operation 0υ, aS is executed, if 1] is 1, the operation I is executed, and if 1 is not 0 or l, the operation α is executed.

(Ill <Second counting means> With Nx-L as nod (modulo), the second count variable is counted every time the first count variable 1 becomes O (every time Q new speed detection values S are obtained). ■Count and amplify 2.

Memory output value creation means> Contents of register variable y [m+1] V After sequentially transferring to [m] (m=o, 1......

(P =+2+Px(lIIod N
)] ++ Memory value group M[J-n L
(mod NxL) ] (n= 1.-.=.

Put the latest memory output value calculated by the following formula using N, ) into V[Pxl.

Nx V [Pxl =ΣWn-M[J-nL(IlodNx
L)]...(5) Here, the value of Wn is +21.
+31 formula and (4) formula are satisfied. That is,
Obtain a group of Px+1 consecutive memory output values from V[Pxl to V[0].

At this time, if the integer J in formula (5) when calculating V[Pxl is Jl, and the integer J in formula (5) when calculating ■[0] is J2, then J, = J2 +Px There is a relationship between Next, the memory output value v0 used first in the control signal generation means is set to V[Px-H (V o -V
[P x 1 ]).

After that, the operation returns to (8).

Q31 <Update storage means> After sequentially transferring the contents of register variable X[m+1] to X[ml (m=o, 1, 2, etc.).

2Kd-1), Enter the composite value calculated and combined at a ratio of 1 (X [2Kd] -E+V [01), that is,
Obtain 2Kd+1 consecutive addition values (addition values of memory output value and rotation error) from X[2Kd] to X[0]. N
Calculate the integer K by subtracting Kd from the second count variable (2) with xL as sod. [K-12-Kd(IIlo
dNxL)ko. Next, X [ml to a predetermined positive ratio Cm
A new update value is obtained by adding and combining the values multiplied by (rr+=o, 1.-.2Kd), and the memory value M [
K] until the next update. That is, 1]-Q. Here, the ratio Cm has the following relationship.

CCm=C2Kd-(m=0.1....z
Kd)...(7) 1]mQ After that, the operation returns to (8).

α reel cycle response means> Digital signal 1 of the reel rotation detector 13 is input, and the reel rotation detection value Ld (digital value) corresponding to the signal 1 is input.
get. Here, Ld is proportional to the rotation period of the reel. Next, the value of Ld is set to the basic memory length as described above. After that, the operation returns to (8).

As in this embodiment, an operation for taking a weighted average is inserted into the update storage means, and the first memory output value V0 (V[
Pxl) and the second memory output value v[0] of the memory output value creation means used in the update storage means (V[Pxl is ahead of v[0]). It was confirmed that the operation of the entire control system became stable. In particular, Px and Qa related to the timing of use
The value of is deeply related to the value of Q, and (QPx-Qa)≧Q/2
I also found out that it is better to do this. This means that the timing at which the same memory output value (for example, the value of V[0]) of the memory output value generation means is used in the control signal generation means is determined by the number of times of detection by the speed detector compared to the timing at which the same memory output value (for example, the value of V[0]) is used in the update storage means. When converted, it means to be faster by Q/2 times or more.

Furthermore, as shown in this embodiment, if the timings of the operation of the memory output value creation means and the operation of the update storage means are shifted with respect to the detection signal of the speed detector, the amount of time required within one detection period of the speed detector can be changed. The amount of calculation is reduced. In particular, when the operation of the memory output value creation means or the update storage means includes many transfers and multiplications, the effect of reducing the amount of calculation required within one detection cycle of the speed detector is big,
Restrictions on hardware operating speed are relaxed.

Furthermore, since the memory output value generation means operates when 1,=O, the memory output value V is used in the control signal generation means. will be changed without delay.

FIG. 6 shows a flowchart of another program for the compensator 4 that takes into consideration the stability of the entire control system.

Here, improvements have been made in the method of calculating memory output values in the memory output value creation means and the number of memory output values to be prepared, as well as the way in which the memory output values of the memory output value creation means are used in the control signal creation means. Further, the zero-order operation that reduces the amount of calculation required within one detection period of the speed detector 3 will be explained in detail. (The overall configuration is the same as that in FIG. 3, and the explanation will be omitted.)
It inputs the output signal q of , and waits for the signal q to become "H". In other words, the speed detector 3 detects (half) the AC signal a.
It detects the period and monitors the output of a new digital signal. When q becomes "H", the digital signal of the speed detector 3 is read, and the speed detection value S (digital value) corresponding to the digital signal is changed, and the reset signal r is set to "H" for a predetermined period of time to increase the speed. Reset the flip-flop 40 of the detector 3. Predetermined reference value 5r
The speed detection value S is subtracted from ef, and the value is multiplied by R (here, R is a predetermined positive constant) to calculate the current rotational error E of the cab scan motor 1.

[E=R・(Sref −3)] αD <Control signal generation means> Memory output value v0 by memory output value generation means described later
and the current rotational error E at a predetermined ratio D:1 to calculate the control signal value Y (Y=E+D −Vo),
The control lI signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the Y value.

aη First Counting Means> With Q as mod, the first count variable 1 is counted up each time a new speed detection value S is obtained. ■1 is Qa (here, Qa is an integer smaller than Q)
The memory output value becomes equal to■. is changed to V[Pxl (described later), and if 1] is not equal to Qa, such a changing operation is not performed.As a result, in the range of I H < Q a, v0=v[Px-1] (described later) ), and 1]≧Q
In the range of a, v0=V[Pxl. moreover,
If 1] is O, then (2), execute the α threat action, and 1] is 1.
If so, the operation Qal is executed, and if 1] is not 0 or 1, the operation (21) is executed.

α■ <Second counting means> When Nx-L is...od (modulo), the second count is performed every time the first count variable 1] becomes 0 (every time Q new speed detection values S are obtained). Count up variable 12.

α sacrifice <Memory output value creation means> After transferring the contents of register variable X [m+1] to X [m] in order,
-1) Calculate the integer J by adding Px+Kd (Px is an integer greater than or equal to 1 and less than or equal to 3, and Kd is an integer greater than or equal to 1) to the second count variable 12 with NxL as mod [
J = + 2 + P x + Q x (+wod
NxL)] - Nx memory value group M [J
-nL (mod Nx L) ] (n-1°・
..., Nx), and enter the value calculated by the following formula into X [2Kd].

Nx X [2Kd] =ΣWn-M[J-nLnzen! (modNxL)] (9) Here, the value of Wn satisfies equations (2), (3), and (4).

That is, 2K consecutive from X[2Kd] to X[0]
d+1 calculated values (calculated values obtained from Nx memory values separated by L intervals) are obtained. Next, register variable y
After sequentially transferring the contents of [m+1] to V [m] (
m=o.

1, --------, Px-1), X [m] (m=
0.1°...2Kd) to a predetermined positive ratio Cm
(m=Q.

Obtain the latest memory output value by adding and combining the values multiplied by 1, ..., 2Kd) and put it in V[Pxl.

-l Here, the ratio Cm has the relationship of equations (7) and (8).

That is, PX+1 consecutive from V[Pxl to v[0]
memory output values are obtained. At this time, substantially V[
Let the integers J and Jl in equation (9) when calculating Pxl,
If the integer J in formula (9) when calculating v[0] is J2, then J.

There is a relationship of =J2+Px. That is, there is a difference between V[Pxl and V[0] corresponding to the integer Px. Next, the memory output value V0 is set to V[Px+1] (■. -V
[Px+1]), and then returns to the operation of a9.

<Update storage means> Calculate an update value by calculating and combining the old memory output value v[0] created by the memory output value creation means and the rotation error E at a ratio of 1:1, and calculate the second count. Update the memory value M[[2] in the RAM area corresponding to variable ■2 M[+
2] =E+■[0]), stored and saved until the next update. After that, the operation returns to a9.

(21) <Reel cycle response means> Inputs the digital signal I of the reel rotation detector 13 and calculates the reel rotation detection value Ld (digital value) corresponding to the signal 1.
get. Here, Ld is proportional to the rotation period of the reel. Next, the value of Ld is set to the basic memory length as described above. After that, the operation returns to (21).

As in this embodiment, an operation for taking a weighted average and an operation for preparing a plurality of memory output values are inserted into the memory output value generation means, and the first memory of the memory output value generation means used in the control signal generation means is inserted. Output value Vo (V [P
x]) and the second memory output value v[0] of the memory output value creation means used in the update storage means (V[Px] is ahead of v[0]). By doing so, the operation of the entire control system will be stable. In this case as well, it is better to set (QPx-Qa)≧Q/2.

It should be noted that calculations using the ratios Wn and Cm are not limited to the above-mentioned forms, and may be any form that substantially realizes the content of the above-mentioned program, and it goes without saying that various equivalent expression transformations are possible. stomach.

Furthermore, when a new rotation error is obtained, the control signal generation means first outputs a new control signal, and then the memory output value generation means calculates the memory output value to be used at the next sampling point. If this is done, the calculation time of the memory output value creation means can be lengthened, and the time delay until the control signal is output can be shortened.
It is easy to ensure the stability of the control system.

In each of the above embodiments, only the rotational speed of the capstan motor is detected by the speed detector, but in addition to this, the rotational phase of the capstan motor is detected by a well-known phase detector, and the two are combined. It goes without saying that this may be considered a rotation error and is included in the present invention. Also,
The output of the compensator may be a digital signal or a PWM signal (pulse width modulation signal), or the output signal of a power amplifier (driving means) may be a PWM signal. Furthermore, a brushless DC capstan motor may be used as the capstan motor.Furthermore, the compensator may be configured with complete hardware such as a PLA (programmable logic array) and perform the same operation as the program described above. Alternatively, analog calculation elements may be used, and various other changes can be made without changing the spirit of the invention.

Effects of the Invention The capstan motor control device of the present invention greatly reduces fluctuations in rotational speed due to fluctuations in reel tensile strength.
Additionally, the amount of memory required has been significantly reduced. Therefore, if a capstan motor control device for a video tape recorder is constructed based on the present invention, a high performance video tape recorder can be obtained economically.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing an example of the built-in program of the compensator shown in FIG. 3, FIG. 2 is a configuration diagram of a magnetic tape running system of a video tape recorder, and FIG. 3 is an overall control device for a capstan motor of the present invention. FIG. 4 is a specific configuration diagram of the speed detector shown in FIG. 3, FIG. 5 is a flowchart showing another example of the built-in program of the compensator of the present invention, and FIG. FIG. 7 is a flowchart showing another example of the built-in program of the compensator. 1... Capstan motor, 2... Rotation sensor, 3... Speed detector, 4...
Compensator, 5... Arithmetic unit, 6... Memory, 7... D/A converter, 8... Power amplifier, 10... ...Magnetic tape, 1]...
Detection reel, lla... Take-up reel, llb.
. . . Supply reel, 12 . . . Reel rotation sensor, 13 . . . Reel rotation detector. Name of agent: Patent attorney Toshio Nakao and one other person Figure 4 Figure 5

Claims (8)

[Claims] (1) a rotation sensor that generates an AC signal with a period corresponding to the rotational speed of the capstan motor; a speed detection means that detects the AC signal multiple times per rotation of the capstan motor based on the AC signal of the rotation sensor; and the speed Compensating means for generating a control signal based on the detection signal of the detecting means, and driving means for driving the capstan motor in accordance with the control signal of the compensating means, wherein the compensating means generates a control signal based on the detection signal of the speed detecting means. rotational error detection means for obtaining a rotational error in response to a detection signal; memory means for storing four or more memory values; and producing a memory output value using at least one memory value stored in the memory means. memory output value creation means, and substantially sequentially updating the memory values of the memory means with an update value corresponding to a value obtained by calculating and combining the memory output value of the memory output value creation means and the rotation error of the rotation error detection means; update storage means for storing; a control signal creation means for calculating and combining the memory output value of the memory output value creation means and the rotation error of the rotation error detection means to create the control signal; and a reel cycle response means for increasing or decreasing the number of memory values handled by the memory output value creation means, and each time the speed detection means obtains a new detection signal, the control signal creation means generates a new control signal. and each time the speed detection means obtains Q new detection signals (here, Q is an integer of 2 or more), the update storage means substantially updates one memory value. Capstan motor control device. (2) The memory means stores N_xL (here, N_x is an integer of 1 or more, and L is an integer of 4 or more) memory value groups M[0] to M[N_xL-1], and the update storage means sequentially stores them. M
[0], M[1], ......, M[N_xL-1]
, and the reel cycle responsive means updates the L
Claim No. 1 characterized in that the value of (
The capstan motor control device according to item 1). (3) N_x≧2, and the memory output value creation means is a memory value group M[J-nL (modN_xL)] (n=1,...
. . , N_x) (here, J is an integer), the memory output value substantially corresponding to the value obtained by calculating and combining the memory output values is calculated. Capstan motor control device. (4) The memory output value creation means generates N_x memory values N[J-nL (modN_xL)] (n=1
, ......, N_x) (here, J is an integer), and further, the plurality of consecutive calculated values regarding the integer J are each multiplied by a predetermined ratio. 2. The capstan motor control device according to claim 2, wherein the memory output value is obtained by adding and combining the values. (5) The update storage means obtains an added value by adding the memory output value of the memory output value creation means and the rotation error of the rotation error detection means, and multiplies the plurality of consecutive added values by a predetermined ratio, respectively. 2. A capstan motor control device according to claim 2, wherein a value obtained by adding and combining the values is stored as a new updated value in a memory value of a memory means. (6) Claim (1) characterized in that the reel cycle response means detects the rotation cycle of the take-up reel.
A control device for a capstan motor as described in 2. (7) The operation of the memory output value creation means and the operation of the update storage means are substantially different with respect to the timing of the detection signal of the speed detection means.
The capstan motor control device according to item 1). (8) The capstan motor control device according to claim (7), wherein the memory output value creation means is operated first, and then the update storage means is operated.