JPS62262684A - Controller for capstan motor - Google Patents

Abstract

PURPOSE:To obtain a controller for a capstan motor in which the influences of a torque variation from the motor itself and a tension variation from a reel are simultaneously reduced. CONSTITUTION:A compensator 4 forms a control signal on the basis of a rotation error of the speed signal of a capstan motor 1 from a speed detector 3 and a speed set value and a rotating speed signal of a reel 11 from a reel rotation detector 13, and supplies it to a power amplifier 8. That is, the output of first memory means and the rotation error signal are combined to be calculated, and the memory value of first memory means is altered to be held. The output of the means, the output of second memory means and the rotation error signal are combined to be calculated to form a control signal, and the combined value is altered to be held in the second memory means. Further, the number of the memory value of the first or second means is increased or decreased in response to the reel rotating speed.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a capstan motor control device. Conventional technology A capstan motor control device that detects the rotational speed of a capstan motor using a speed detector and controls the power supplied to the capstan motor based on the detection signal is used in magnetic tape running devices such as video tape recorders. Although it is widely used (for example, see Japanese Patent Application No. 142,724/1982), such control devices only perform proportional, W4, and differential control that have been used in the past. Therefore, it was not possible to sufficiently suppress fluctuations in rotational speed due to fluctuations in load torque. In order to solve such problems, the applicant has filed a patent application filed in 1983.
In Japanese Patent Application No. 0-229143 and Japanese Patent Application No. 60-229144, we proposed a high-performance motor speed control device that is highly resistant to load torque fluctuations. In other words, the patent application 1986-
No. 229143 and Japanese Patent Application No. 60-229144 disclose a rotation sensor that generates an AC signal with a period corresponding to the rotation speed of a motor, and a speed detection means that performs detection multiple times per rotation of the motor based on the AC signal of the rotation sensor. A speed control system is constituted by a compensating means that calculates and stores a control signal based on the detection signal of the speed detecting means and generates a control signal, and a power amplifying means (driving means) that supplies the motor with electric power according to the control signal of the compensating means. are doing. Furthermore, a rotation error detection means for obtaining a rotation error in response to a detection signal of the speed detection means, and a memory means for storing NxL (?jI several) memory value groups M[0] to M[NxL-1]. , a composite value calculation means (memory output value creation means) that substantially calculates a composite value that is compositely calculated using Nx memory value groups spaced apart by L intervals of the memory means, and a composite value of the composite value calculation means. and updating storage means for substantially sequentially updating and storing memory values in the memory means with updated values corresponding to a value obtained by calculating and combining the rotational errors of the rotational error detection means;
A high-performance motor speed control device is realized by using a compensating means having a control signal generating means which generates control number 53 by calculating and combining the composite value of the composite value calculating means and the rotation error of the rotation error detecting means. are doing. Problems to be solved by the invention Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-22914
It has been found that it is necessary to make some improvements when the motor speed control '4'B device shown in No. 4 is used as a capstan motor control device. For example, in the case of a capstan motor in a video tape recorder, it is affected not only by torque fluctuations of the capstan motor itself (of which the bearing is a part), but also by tension fluctuations from the take-up reel (or supply reel). It was found that both speed fluctuations caused by the capstan motor itself and speed fluctuations caused by the reel occurred to approximately the same extent. Furthermore, the frequency of tension fluctuations from the reel changes with its winding diameter. Therefore, patent application No. 60-2291
With the configurations of No. 43 and Japanese Patent Application No. 60-229144, it was not possible to reduce the fluctuations in rotational speed due to the influence of these tension fluctuations. The present invention takes these points into consideration and provides a capstan motor control device that simultaneously significantly reduces the influence of torque fluctuations of the capstan motor itself and the influence of tension fluctuations from the reel. Means for Solving the Problems The present invention includes a rotation sensor that generates an alternating current signal with a period corresponding to the rotational speed of the capstan motor, and a plurality of detections per rotation of the capstan motor based on the alternating current signal of the rotation sensor. the compensating means for generating a control signal based on the detection signal of the speed detecting means; and a driving means for driving the capstan motor in accordance with the control signal of the compensating means. The means includes a rotation error detection means for obtaining a rotation error in response to a detection signal of the speed detection means, a first memory means for storing a plurality of memory values, and at least one memory value stored in the first memory means. a first memory output value creation means that creates a memory output value using one memory value; and a value obtained by calculating and combining the memory output value of the first memory output value creation means and the rotation error of the rotation error detection means. a first update storage means for updating and storing memory values of the first memory means substantially sequentially with update values corresponding to the update values; a second memory means for storing a plurality of memory values; a second memory output value generating means for generating a memory output value using at least one memory value stored in the memory means; and a memory output value of the first memory output value generating means and the second memory output value.
a second memory means for substantially sequentially updating and saving the memory values of the second memory means with an update value corresponding to a value obtained by calculating and combining the memory output value of the memory output value generating means and the rotation error of the rotation error detection means; and a memory output value of the first memory output value creation means, a memory output value of the second memory output value creation means, and a rotation error of the rotation error detection means to generate the control signal. and a reel period responsive means for increasing or decreasing the number of memory values stored in the first memory means by the first update storage means in accordance with the rotation period of the reel. This solves the above problems. Furthermore, the present invention includes a rotation sensor that generates an alternating current signal with a period corresponding to the rotational speed of the capstan motor, and a speed detection means that detects a plurality of times per rotation of the capstan motor based on the alternating current signal of the rotation sensor. , comprising compensation means for generating a control signal based on the detection signal of the speed detection means, and drive means for driving the capstan motor according to the control signal of the compensation means, and the compensation means is configured to generate a control signal based on the detection signal of the speed detection means. a rotational error detection means for obtaining a rotational error in response to a detection signal; a first memory means for storing a plurality of memory values; and at least one memory value stored in the first memory means. a first memory output value creation means for creating a memory output value;
a first memory value for substantially sequentially updating and saving the memory value of the first memory means with an update value corresponding to a value obtained by calculating and combining the memory output value of the memory output value creation means and the rotation error of the rotation error detection means; a second memory means for storing a plurality of memory values; and a second memory for producing a memory output value using at least one memory value stored in the second memory means. output value creation means, the first memory means corresponding to a value obtained by calculating and combining the memory output value of the value creation means, the memory output value of the second memory output value creation means, and the rotation error of the rotation error detection means; a second update storage means for substantially sequentially updating and storing the memory value of the second memory means according to the update value; and a memory output value of the first memory output value creation means and the second memory value.
control signal generation means for generating the control signal by calculating and combining the memory output value of the memory output value generation means and the rotation error of the rotation error detection means; The above-mentioned problem is also solved by configuring the reel to include a reel cycle response means that increases or decreases the number of memory values to be stored in accordance with the rotation cycle of the reel. Operation According to the present invention, a high-performance capstan motor control device is realized by adopting the above-described structure. In other words, Japanese Patent Application No. 1983-229143 and Japanese Patent Application No. 1983-
In the motor speed control device shown in No. 229144, the control characteristics can be improved by using the frequency of torque fluctuation of the capstan motor itself (fixed frequency) and the frequency of tension fluctuation from the detection reel (variable frequency). frequency) so that both frequencies (groups) can be obtained simultaneously. Embodiment An embodiment of the capstan motor control device of the present invention will be described below with reference to the drawings. FIG. 2 shows a basic configuration diagram of the tape running system of a video tape recorder. The magnetic tape 10 fed out from the supply reel Ilb is moved by impedance rollers 22 and 23 to a cylinder motor 21.
It is wrapped more than 180 degrees around. Video information is recorded on and reproduced from a magnetic tape by a rotating air head mounted on a cylinder motor 21. The magnetic tape 10 is pressed against the capstan motor 1 by a pinch roller 24, runs at a predetermined speed proportional to the rotational speed of the capstan motor 1, and is wound around a winding loop 11a. The rotational speed of the capstan motor l fluctuates due to tension fluctuations in the magnetic tape 10 caused by the take-up reel lla and the supply reel llb, causing fluctuations in the magnetic tape running speed (wow, etc.).
fluff) was occurring. Since the frequency of tension fluctuation is proportional to the rotational speed of the reel, it changes according to the same amount of tension applied to each reel of the magnetic tape 10, and the frequency dissipates over a fairly wide range from the beginning to the end of tape winding. Occur. In particular, the rotational speed of the capstan motor l tends to fluctuate greatly due to the influence of the take-up reel lla. Naturally, fluctuations in the torque of the capstan motor itself (for example, fluctuations in the Fj friction torque of the bearing) also cause fluctuations in the rotational speed of the capstan motor.
It was causing wow and fluff. The frequency of torque fluctuation of the capstan motor itself is a constant value that is synchronized with the rotation of the capstan motor. FIG. 3 shows a configuration diagram representing an embodiment of the present invention. In FIG. 3, the rotation sensor 2 is connected to the capstan motor 1.
The 0-rotation sensor 2 generates an AC signal a Z, 4 times (Z9 is an integer of 2 or more; in a capstan motor of a video tape recorder, Z9 = 357) per revolution as the motor rotates. The alternating current signal a is manually input to the speed detector 3, and a digital signal corresponding to the period of the alternating current signal a is obtained. A specific configuration diagram of the speed detector 3 is shown in FIG. The AC signal a is waveform-shaped by a waveform shaping circuit 31,
A shaped signal g is obtained. The shaped signal g is directly inputted to the AND circuit 33 and the first differentiating circuit 36, and is also inputted to the second differentiating circuit 38 via the inverter circuit 37. The first differentiation circuit 36 generates a minute width differentiation pulse i at the rising edge of the shaping signal g, and resets the internal state of the counter circuit 34 by this pulse. The second differentiating circuit 38 generates a differential pulse k of minute width at the falling edge of the shaped signal g, and the second differentiating circuit 38
Load the digital signal j into the latch circuit 39 (input,
data input type flip-flop 4
Set the output to 0. The clock pulse p of the oscillation circuit 32 and the overflow output signal W of the counter circuit 34 are also input to the input side of the AND circuit 33.The 0 oscillation circuit 32 is composed of a crystal oscillator, a frequency divider, etc. A clock pulse p (500kllz) with a frequency much higher than the frequency of g
degree) has occurred. The counter circuit 34 is a 12-bit up counter that counts up the contents every time the output pulse h of the AND circuit 33 arrives. In addition, overflow output (No. 3 W is the counter circuit 34
When the count content of the counter circuit 34 is less than a predetermined value, it is "H", and when the counter content of the counter circuit 34 exceeds a predetermined value, W
changes to "L" (here, "1" represents a high potential state and "L" represents a low potential state).The data input type flip-flop 40 changes to "L" at the falling edge of the shaping signal g. “H” input to the data input terminal at the edge point
Take in the output Q and set it to “H” (q=“H”)
. Furthermore, when the rate signal r from the compensator 4 becomes "Ho", the internal state of the flip-flop 40 is reset (
q-“L”). Next, the operation of the speed detector 3 shown in FIG. 4 will be explained. Assume now that the flip-flop 40 has been reset by a reset signal r. When the output signal g of the waveform shaping circuit 31 changes from "L" to "H", the first differentiation circuit 36 first generates a differentiation pulse i and resets the counter circuit 34. Then, the output signal of the AND circuit 33 The clock pulse p of the oscillation circuit 32 is output as a signal, and the counter circuit 34 counts the output signal and changes its internal state.Next, the output signal g of the waveform shaping circuit 31 becomes "H". When the output signal changes from " to "L," the output signal of the AND circuit 33 becomes "L', and the counter circuit 34 maintains its internal state. Further, the second differentiation circuit 38 outputs a differentiation pulse k, loads the state signal j of the counter circuit 34 into the latch circuit 39, and changes the output signal q of the flip-flop 40 from "L" to "
Change it to H. Therefore, the digital signal S of the latch circuit 39 has a value proportional to the (half) period length of the AC signal a of the rotation sensor 2, and is inversely proportional to the rotational speed of the capstan motor l. A compensator 4, which will be described later, looks at the output signal q of the flip-flop 40, and when q becomes "H", outputs a digital signal from the launch circuit 39, and then outputs a reset signal r to "H" for a predetermined short period of time. ” to reset the flip-flop 40 to the initial state. Note that when the rotational speed of the capstan motor l is too slow, the internal state of the counter circuit 34 is set to a predetermined value because the period of the output signal g of the waveform shaping circuit 31 is long. When the value exceeds the value, the overflow output signal W changes from "H" to "Yes", the output signal of the AND circuit 33 becomes "1L", and the counter circuit 34 may hold a predetermined large value. The reel rotation sensor 12 in FIG. 3 generates an alternating current signal e in response to the rotation of the detection reel (take-up reel or supply reel) 1. The reel rotation detector 13 obtains a digital signal 1 proportional to the period of the alternating current signal e. Its specific configuration example is the same as the speed detector 3 shown in FIG. 4 (without the flip-flop 40).The compensator 4 in FIG. It is constituted by a D/A converter 7, inputs the digital signal of the speed detector 3 and the digital signal 1 of the reel rotation detector 13, calculates and processes it using a built-in program described later, and outputs the control signal C. Compensation The control signal C of the device 4 is input to the power amplifier 8 (driving means), and the power amplified drive signal d (current proportional to the control signal C) is supplied to the capstan motor l. A speed control system is constituted by the rotation sensor 2, speed detector 3, compensator 4, and power amplifier 8 (driving means), and the rotation speed of the capstan motor 1 is controlled to a predetermined value.The memory of the compensator 4 6 is divided into a ROM area (ROM: read-only memory) in which predetermined programs and constants are stored, and a RAM area (RAM: random access memory) in which necessary values are stored.The arithmetic unit 5 is located in the ROM area. Predetermined operations and calculations are performed according to the program.First
The figure shows a specific flowchart of the program. Next, the operation will be explained in detail. (1) <Rotation error detection means> First, the arithmetic unit 5 uses the flip-flop 40 of the speed detector 3.
The output signal q is manually inputted and is waiting for the signal q to become "H". In other words, the speed detector 3 detects (half) the AC signal a.
It detects the period and monitors the output of a new digital signal. When q becomes "H", the digital signal of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal is reset, and the ε signal is set to "H" for a predetermined period of time. to reset the flip-flop 40 of the speed detector 3.Predetermined reference value 5
Subtract the speed detection value S from ref, multiply that value by R (here, R is a predetermined positive constant), and calculate the current rotational error E of the capstan motor 1 [E=R・(Sr.
ef-3)]. (2) <Control signal creation means> Memory output value ■ by the first memory output value creation means. (
(described later), memory output value y+ by the second memory output value creation means, (described later), and current rotation error E at a predetermined ratio p.
:[)':l'Here, D, D' are O<D, D'≦
A constant of 1, preferably D=D'-1), is used for calculation synthesis and control? 1] Calculate the signal value Y (Y=E+D −V0
+D'・V'. The L control signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (3) <First counting means> Nx - L (-Finally, Nx is an integer, L is an integer of 4 or more, here, it is preferable that Nx is an integer of 2 or more, so from now on such cases ) to explain the steel od
(method), the first count variable ■ is counted up every time a new speed detection value S is obtained, that is, l
=[↓After setting it to l, if r=NxL, reset 1 to 0. If you perform such an operation, I will be from 0 to Nx
It becomes an integer between L-1. Note that the initial value of ■ is NxL-
1, and the initial value of L is a predetermined large integer. Also,
The value of L is changed at any time by reel cycle response means, which will be described later. (4) <First memory output value creation means> Set the integer J equal to 1, and (J-1), create Nx memory value groups M[J-nL (sod NxL) separated by L intervals in the RAM area. )
] Using (n=1.-.=.N,), the memory output value ■ is determined by the following formula. create. Nx...fll Here is the ratio W. The value of is 0×Wn×2/N×(n=1.....,Nx)・
...(2), and is further standardized as Nx. Specifically, in the case of 2 above Nx, Wn = 1/Nx (n” 1.----, Nx)
......(4) Then, the fll expression is a memory value group M[J-nL(sod
NxL) ] (n = 1, --, Nx) is simply added and combined and then divided by Nx (an integer), making the operation very simple (however, this is not limited to this case). (5) <First update storage means> Memory output 1tIv by the first memory output value creation means
0 and the rotation error E are calculated to calculate an update value, and the memory value M [
Update +1 and CM [B=E1V. ), stored until the next update. (6) <Second counting means> N18 ・L' (Generally, N'8 is !1 loss, L' is 4
Since it is preferable that the above integer, here N18, be an integer of 2 or more, such a case will be described below. ) as mad (modulus), the second count variable Bi is counted and amplified every time a new speed detection value S is obtained, that is, after setting Bi=Bi+1, I l = N
1. If Ll then l. Reset to 0. If you perform such a calculation, ■
゛ is an integer between O and N'xL'-1. In addition, L
" is a constant integer corresponding to the rotation period of the capstan motor. (Ill always, L゛ is an integer multiple of Zq). (7) <Second memory output value creation means> Integer J° to I゛equally J"-I"), a group of N' memory values M'[J'-nL' spaced L' apart in the RAM area.
(modN'x L') (n=1゜・・・・・・,
N'x) is used to create the memory output value V''. by the following formula. (shod N' x L') ] ・・
...(5) Here, the ratio W'. The value of is 0 <w',<2/N'x(n"1."""+N'
)0...(6) and is further standardized as . Specifically, in the case of N'8≧2, w'n-1/N'x (n=1+-...-+N'x)・
...(8) Then, equation (5) becomes the memory value group M'[J'-nM(
eAod N'xL')] (n=1.--, N'
x) are simply added and combined and then divided by N'X (an integer), which makes the calculation very simple (however, this is not limited to this case). (8) <Second update storage means> Memory output value v0 by the first memory output value creation means and memory output value V' by the second memory output value creation means. and rotation error ε are calculated to calculate an updated value, and the memory value M' in the ram area corresponding to the second count variable l' is calculated.
Update [B] M゛[B] = E+V. ＋■゛. ),
Stored until the next update. (9) <Reel period responsive means> Digital signal 1 of the reel rotation detector 13 is inputted, and a reel rotation detection value d (digital value) corresponding to the signal l is obtained. Here, L is the 0th order which is proportional to the rotation period of the reel, and is the first basic that determines the number of memory values used in the first memory output value creation means and the first update storage means. memory length) is changed to the reel rotation detection value Ld. After that, the operation returns to (1). If configured in this way, the detection reel 1] (S-
The rotational speed of the capstan motor 1 hardly changes with respect to the tension fluctuation that occurs on the supply reel 11 or the supply reel 11b. This means that the first basic memory length is changed at any time by the reel cycle response means to a value proportional to the rotation cycle of the detection reel, and the number N of memories handled by the first update storage means and the first memory output value creation means This is because the number L (the number of memory values stored in the first memory means) changes, and the frequency at which the control characteristic improvement effect appears can always be adjusted to the frequency corresponding to the rotation period of the detection reel. (Refer to the earlier patent for the effect of improving the control characteristics.) In other words, regardless of the winding diameter of the detection reel 1, the control characteristics of the capstan motor at the frequency of the tension fluctuation of the detection reel 1 (disturbance suppression characteristics) ) can be improved. Therefore, detection reel 1
] Even if a large tension fluctuation occurs, the rotational speed of the capstan motor 1 will not fluctuate. Incidentally, since the influence of the tension fluctuation of the take-up reel lla was large on the capstan motor l, it can be said that it is preferable to select the take-up reel lla as the detection reel 1]. Furthermore, in this embodiment, rotational speed fluctuations due to torque fluctuations of the capstan motor itself are almost completely eliminated. This is because the second basic memory length L° is set to a constant value corresponding to the rotation period of the capstan motor, and the number of memories handled by the second update storage means and the second memory output value creation means is N'xL. ' (the number of memory values stored and saved in the second memory means) is constant, and by these operations, it is possible to obtain the effect of improving the control characteristics even at a frequency corresponding to the rotation period of the capstan motor. This is because it is possible. Therefore, in this embodiment, the influence of torque fluctuations of the capstan motor itself and the influence of tension fluctuations from the reel are simultaneously significantly reduced, and the rotational speed of the capstan motor is significantly reduced. Figure 5 shows a compensator 4 that takes into account the stability of the entire control system.
Here, the first program flowchart is shown.
and the method of calculating the update value in the second update storage means, the number of memory output values to be prepared in the first and second memory output value creation means, and the first and second memory outputs in the control signal creation means. The method of using the memory output value of the value creation means has been improved. Next, the operation will be explained in detail. (The overall configuration is the same as in Figure 3,
(Description omitted). aO <Rotation error detection means> First, the arithmetic unit 5 is the flip-flop 40 of the speed detector 3.
inputs the output signal q of the AC signal a, and waits for the signal q to become "Ho".In other words, the speed detector 3 outputs (half) of the AC signal a.
It detects the period and monitors the output of a new digital signal. When q becomes "H", the digital signal of the speed detector 3 is read, and the speed detection value S (digital value) corresponding to the digital signal is changed, and the reset signal r is set to "Ho" for a predetermined period of time to detect the speed. The flip-flop 40 of the device 3 is reset to a predetermined reference value 5r.
Subtract the speed detection value S from ef, multiply that value by R (here, R is a predetermined positive constant), and calculate the current rotational error E of the capstan motor l [E"=I?・(Sr.
ef-3) ]. aZ <Control signal generation means> Memory output value V[P by the first memory output value generation means
X] (described later), the memory output value V'[P'x] (described later) by the second memory output value creation means, and the current rotation error E at a predetermined ratio D:D':1, Calculate the control signal value Y (Y=E+D −V [r'x]
+D'-V'CP'x]). The control signal value Y is output to the D/A converter 7 and converted into a DC voltage (control signal) corresponding to the value of Y. (1m <first counting means> Nx-L is 1lod C method), and each time a new speed detection value S is obtained, the first count variable I is counted up. For example, it is changed at any time to an integer corresponding to the rotation period of the detection reel by the operation of a reel period responsive means, which will be described later. aa <First memory output value creation means> After sequentially transferring the contents of the register variable V[m+l] to V[ml (m=0.L,...P, -1), NxL Calculate the integer J by adding PX (here, Px is an integer greater than or equal to 1 and less than or equal to 6, and Px = 3 is preferable) to the first count variable I with sod [J=I+PX (madNxL)]. The first memory value group M [J-n L (mad NxL
)] (n=1.-.Nx) and put the latest memory output value calculated by the following formula into V[PX]. Nx (+mod NxL) ] −・m=91 Here,
The value of Wo satisfies equations (2) and (3). That is, a first memory output value group of pX'+1 consecutive from v[PX] to ■[0] is obtained. At this time, if the integer J in formula (9) when calculating V[PX] is Jl, and the integer J in formula (9) when calculating ■[0] is J2, then J, = J2 + PX There is a relationship between α data <First update storage means> After sequentially transferring the contents of register variable X[m+l] to χ[ml (m=0.1.2...2Kd-1), [2Kd] (here, K is an integer, preferably K = 3) is calculated by combining the old memory output value ■[0] created by the first memory output value creation means and the rotation error E. Enter the composite value (X [2, ] = E+V [0]. In other words, from X [2, ] to

2 consecutive to [0],
+1 additional value (addition value of the memory output value of the first memory output value creation means and the rotation error) is obtained. Calculate the integer K by subtracting Kd from the first count variable vI+ with NxL as mod [K=I Kd(sod Nx L) ]-
Next, a predetermined positive ratio Cm (m=o, 1
．． ......, 2K), and obtain a new updated value by adding and combining the multiplied values, and obtain the memory value M [K] in the RAM area.
It will be stored and saved until the next update. That is, m=6. Here, the ratio Cm has the following relationship. Cm=C2Kd-m(m-0,1,・old・・Kd)・
...tll) m=Q 0]9 <Second counting means> With N'8・Lo as mod, count up the second count variable Bi every time a new speed detection value S is obtained. I will do it. Note that Lo is a constant value corresponding to the rotation period of the capstan motor. (Normally, L" is an integer multiple of Z9). Second memory output value creation means> After sequentially transferring the contents of the register variable V'[m+1] to V'[ml (m=0.1. ...IP'x
-1), N'xL' is l1od, and the second count variable Bi is added Pl, (here, plX is an integer greater than or equal to 1 and less than or equal to 6, and p +, = 3 is preferable), which is the integer J'. Calculate [J゛; Bi+P' x (mod N'
x L')] *Second memory value group M' in the ram head area
(J'-nL'(fflodNIXLo)](n=1
．．・Old..., NIX), enter the latest memory output value calculated by the following formula into V'[P'x]. (+mod N' x L') ] '・
'``' ``Here, W''. Values are [6) and (7)
satisfies the formula. That is, from V"[P'X] to V'
A first memory output value group of p +, +1 consecutive to [0] is obtained. At this time, when calculating V'[P'x], the integer J° in the o3 formula is set to Jll, and V' [0]
If the integer J゛ in the Q1 formula when calculating is J12, then
J1]=J'2+P'. (2) <Second update storage means> After sequentially transferring the contents of the register variable X"[m+l] to X'[ml... ', -1), X'[2 to',] (here, K1
6 is an integer, and preferably = 3), the output value V[Px] created by the first memory output value creation means
(Or input the old memory output value ■ by using V [0] and the second memory output value creation means. Enter the composite value obtained by calculating and combining [0] and the rotation error E. (
X'[2',] =E+V [PX3 +V'
[0], that is, from X'[2K'd] to X' [0
], an additional value of +1 (addition value of the memory output value of the first memory output value creation means, the memory output value of the second memory output value creation means, and the rotation error) is obtained. N'
K1 from the first count variable ■° with xL' as sod
Calculate the integer K'' by subtracting 6 [K゛==bee a (a
+odN'xL')] - Next, the value obtained by multiplying X' [ml by a predetermined positive ratio C'm (m-0, l. . . ., 2 and 'd) is added and synthesized. Obtain the new updated value and update the memory value M'[K'
1 and is stored until the next update. In other words, m!
O, where the ratio C'm has the following relationship. C'm-1C' 2 K' d-z (m ” O
+ 1 + "・"・lK', 1...05
) m=(1 aS <Reel cycle response means> Digital signal 1 of the reel rotation detector 13 is input, and the reel rotation detection value corresponding to the signal 1 is (digital value)
get. Here, L is the zeroth order which is proportional to the rotation period of the reel, and the first basic memory length which determines the number of memory values used in the first memory output value creation means and the first update storage means. ) value as the reel rotation detection value and change it to . After that, the operation returns to all. In addition, the ratio W. , W', , Cm, and C'm are not limited to the above-mentioned form, and may be any form that substantially realizes the contents of the above program, and various large isometric transformations are possible. Needless to say, when a new rotation error is obtained, the control signal generating means first outputs a new control signal, and then outputs the first and second signals to be used at the next sampling point. If the memory output value of the memory output value creation means is calculated, the calculation time of the first and second memory output value creation means can be lengthened, and the time delay until the control signal is output can be shortened. It is easy to ensure the stability of the control system. Furthermore, in each of the above-mentioned embodiments, the first basic memory length is changed at any time by the reel period response means to a value proportional to the rotation period of the detected reel, and the first update storage means and the first memory output value are created. Number of memories handled by the means NxL
(the number of memory values to be stored and saved in the first memory means), and with the second basic memory length L° constant, the number of memories handled by the second update storage means and the second memory output value creation means N 'xL' (the number of memory values stored in the second memory means) was fixed. However, it goes without saying that such a relationship may be reversed; that is, the second basic memory length L° may be changed at any time by the reel cycle responsive means to a value proportional to the rotation cycle of the detection reel. The number of memories N'xL' (
The number of memory values to be stored and saved in the second memory means is changed, and the number of memory values NxL (the number of memory values to be stored and saved in the second memory means) handled in the first update storage means and the first memory output value creation means is changed while the first basic memory length is kept constant. The effect of the present invention can also be obtained even if the number of memory values stored in one memory means is fixed. (9) Or Q
If the first basic memory length of No. 9 is replaced with the second basic memory length L', the result can be simply obtained, so illustration thereof will be omitted. Furthermore, in each of the above embodiments, only the rotational speed of the capstan motor is detected by the speed detector.
In addition to this, the rotational phase of the capstan motor may be detected by a well-known phase detector, and both may be combined to obtain a rotational error, which is, of course, included in the present invention.
Furthermore, the output of the compensator may be a digital signal or a PWM signal (pulse width modulation signal), the output signal of a power amplifier (driving means) may be a PWM signal, or a brushless DC capstan motor may be used as the capstan motor. In addition, the compensator may be configured with complete hardware such as a PLA (programmed pull logic array) to perform the same operation as the program described above. In addition, various modifications may be made without changing the gist of the present invention. Effects of the Invention In the capstan motor control device of the present invention, fluctuations in rotational speed due to fluctuations in the torque of the capstan motor itself and fluctuations in the torque of the capstan motor itself are simultaneously significantly reduced. Therefore, if a capstan motor control device for a video tape recorder is constructed based on the present invention, a high performance video tape recorder can be obtained.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a flowchart showing an example of the built-in program of the compensator shown in FIG. FIG. 4 is a block diagram of the entire capstan motor control device, FIG. 4 is a specific block diagram of the speed detector shown in FIG. 3, and FIG. 5 is a flowchart showing another example of the built-in program of the compensator of the present invention. It is a diagram. 1... Capstan motor, 2... Rotation sensor, 3... Speed detector, 4...
Compensator, 5...7, 2''i, 6...
Memory, 7...D/A converter, 8...
Power amplifier, lO...Magnetic tape, 1]...
...Detection reel, lla...Take-up reel, l
lb... Supply reel, 12... Reel rotation sensor, 13... Reel rotation detector.

Claims (8)

[Claims] (1) a rotation sensor that generates an AC signal with a period corresponding to the rotational speed of the capstan motor; a speed detection means that detects the AC signal multiple times per rotation of the capstan motor based on the AC signal of the rotation sensor; and the speed The compensation means generates a control signal based on the detection signal of the detection means, and the drive means drives the capstan motor according to the control signal of the compensation means, and the compensation means generates a control signal based on the detection signal of the speed detection means. rotational error detection means for obtaining a responsive rotational error; first memory means for storing a plurality of memory values; and a memory output value using at least one memory value stored in the first memory means. The first step is to create
and the first memory output value generating means by an updated value corresponding to a value obtained by calculating and combining the memory output value of the first memory output value generating means and the rotation error of the rotation error detection means.
a first updating/storing means for substantially sequentially updating and saving memory values of the memory means; a second memory means for storing a plurality of memory values; and at least one memory value stored in the second memory means. a second memory output value creation means for creating a memory output value using one memory value; a memory output value of the first memory output value creation means; and a memory output value of the second memory output value creation means. and a second updating/storing means for substantially sequentially updating and storing the memory values of the second memory means with an updated value corresponding to a value obtained by calculating and combining the rotational errors of the rotational error detection means; control signal generation means for generating the control signal by calculating and combining the memory output value of the memory output value generation means, the memory output value of the second memory output value generation means, and the rotation error of the rotation error detection means; 1. A control device for a capstan motor, comprising a reel cycle response means for increasing or decreasing the number of memory values stored in the first memory means by the first update storage means in accordance with the rotation cycle of the reel. (2) The number of first memory means is N_xL (here, N_x
is an integer greater than or equal to 1, and L is an integer greater than or equal to 4).
0] to M[N_xL-1], and the first update storage means sequentially stores M[0], M[1], . . . , M[N
_xL-1], and the value of L is changed by a reel cycle responsive means. (3) The reel cycle response means detects the rotation cycle of the take-up reel or the supply reel, and sets a value of L that is proportional or approximately proportional to the detection cycle. The capstan motor control device according to item (2). (4) N_x≧2, and the first memory output value creation means is a memory value group M[
J-nL (mod N_xL)] (n=1,...
. , N_x) (here, J is an integer), the memory output value substantially corresponds to the value obtained by arithmetic synthesis. Capstan motor control device. (5) a rotation sensor that generates an AC signal with a period corresponding to the rotation speed of the capstan motor; a speed detection means that detects the AC signal multiple times per rotation of the capstan motor based on the AC signal of the rotation sensor; The compensation means generates a control signal based on the detection signal of the detection means, and the drive means drives the capstan motor according to the signal of the compensation means, and the compensation means generates a control signal based on the detection signal of the speed detection means. rotation error detection means for obtaining a responsive rotation error; first memory means for storing a plurality of memory values; and at least one memory value stored in said first memory means.
a first memory output value creation means that creates a memory output value using the memory values of the memory; a first memory means for substantially sequentially updating and saving memory values of said first memory means with corresponding update values;
a second memory means for storing a plurality of memory values; and a second memory for producing a memory output value using at least one memory value stored in the second memory means. an output value creation means, and a value corresponding to a value obtained by calculating and combining a memory output value of the first memory output value creation means, a memory output value of the second memory output value creation means, and a rotation error of the rotation error detection means. a second updating/storing means for substantially sequentially updating and saving the memory value of the second memory means according to the updated value; and a memory output value of the first memory output value creating means and the second memory output value. control signal generating means for generating the control signal by calculating and combining the memory output value of the generating means and the rotation error of the rotation error detecting means; and a memory that is stored and saved in the second memory means by the second update storage means. 1. A control device for a capstan motor, comprising a reel cycle responsive means for increasing or decreasing the number of values in accordance with the rotation cycle of a reel. (6) The number of second memory means is N'_xL' (here, N
'_x is an integer greater than or equal to 1, L' is an integer greater than or equal to 4), the memory value group M'[0] to M'[N'_xL'-1] is stored, and the second update storage means sequentially stores M' [0], M'[1],
. . . M'[N'_xL'-1], and the value of L' is changed by a reel cycle responsive means. A control device for a capstan motor as described in 2. (7) The reel period response means detects the rotation period of the take-up reel or the supply reel, and sets a value of L' that is proportional or approximately proportional to the detected period. The capstan motor control device according to item (6). (8) N'_x≧2, and the second memory output value creation means creates a group of memory values M'[J'-nL' (mod N'_xL') separated by L' intervals of the second memory means. ](n=
1, ......, N'_x) (here, J' is an integer)
7. The capstan motor control device according to claim 6, wherein the memory output value substantially corresponds to the value obtained by calculating and combining the above.