JPH04208083A - Motor speed controller - Google Patents

Abstract

PURPOSE:To relieve restriction of the processing time of the title controller by a method wherein a speed detecting means which performs a plurality of detections for one turn of a motor, a compensating means which generates control signals with a first processing means and a second processing means, etc., are provided and the first processing means and the second processing means are operated in parallel with each other. CONSTITUTION:A DC motor 1 drives a rotary sensor 2 and a load 14 directly to rotate. A speed detecting means 3 which performs a plurality of detections for one turn of the motor 1 with an AC signal from the rotary sensor 2, a compensating means 4 which generates control signals with a first processing means 8 and a second processing means 9 and a driving means 13 which drives the motor 1 in accordance with the control signals from the compensating means 4 are provided. The first processing means 8 and the second processing means 9 are operated practically in parallel with each other. In other words, the processings from the detecting operation of the speed detecting means 3 to the control signal generation of the control signal generating means are shared by the first processing means 8 and the second processing means 9 and the respective processing means are operated in parallel with each other with predetermined timings. With this constitution, the processing time can be reduced.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a motor speed control device.

Conventional technology Motor speed control devices that detect the rotational speed of a motor using a speed detector and control the supply signal to the motor using the detection signal are widely used in capstan motors of video tape recorders, cylinder cylinders, etc. (See, for example, Japanese Patent Application No. 56-142724). However, such speed control devices only perform proportional, integral, and differential control that has been used in the past.
It was not possible to sufficiently suppress rotational fluctuations due to load torque fluctuations.

In order to solve such problems, the patent application 1986-229
No. 143 and Japanese Patent Application No. 60-229144 propose a high-performance motor speed control device that is highly resistant to load torque. That is, patent application No. 60-2291
No. 43 and Japanese Patent Application No. 60-229144 disclose a rotation sensor that generates an alternating current signal with a period corresponding to the rotational speed of the motor, a speed detection means that performs detection multiple times per motor rotation based on the alternating current signal of the rotation sensor, A speed control system is constituted by a compensating means that calculates and stores a control signal based on the detection signal of the speed detecting means, and a power amplifying means that supplies the motor with electric power according to the control signal of the compensating means. Furthermore, a rotation error detection means for obtaining a rotation error in response to a detection signal of the speed detection means, and a memory means for storing N, L (plurality) of memory value groups M[0] to M[NXL-1]. , a composite value calculating means that substantially calculates a composite value that is compositely calculated using NX memory value groups separated by L intervals of the memory means, and a composite value of the composite value calculating means and rotation of the rotation error detecting means. update storage means for substantially sequentially updating and storing memory values in the memory means with update values corresponding to the values obtained by calculating and combining the errors; and calculating and combining the combined value of the combined value calculation means and the rotational error of the rotational error detection means. By using a compensating means having a control signal generating means for generating a control signal based on the compensating means, a high performance motor speed control device is realized.

Problems to be Solved by the Invention However, in the above-mentioned Japanese Patent Application No. 60-229143 and Japanese Patent Application No. 60-229144, the composite value calculation means (
The operation of the compensation means, including the memory output value creation means) and the update storage means, requires a considerable amount of calculation, and in order to complete the specified calculation within the detection period of the speed detector, expensive high-speed multipliers, etc. are required. It was necessary to perform high-speed calculations using . That is,
There were considerable restrictions regarding the configuration and operating speed of the hardware that implements the compensation means.

The present invention takes these points into consideration and is devised to relax the constraints on calculation time.

Means for Solving the Problems The present invention provides rotation sensor means for generating an alternating current signal with a period corresponding to the rotational speed of a motor, and speed detection means for detecting a plurality of times per rotation of the motor based on the alternating current signal of the rotation sensor means. and compensating means for generating a control signal using the first calculating means and the second calculating means, and driving means for driving the motor in accordance with the control signal of the compensating means, and the first calculating means is provided with a speed detecting means. a rotation error detection means for obtaining a rotation error according to a detection signal of the rotation error detection means; a control signal generation means for generating a control signal by calculating and combining the memory output value and the rotation error of the rotation error detection means; and a timing signal of the second calculation means. The second calculation means has a memory means for storing four or more memory values, and a memory output using at least one memory value stored in the memory means. a memory output value creation means for creating a value, a composite error creation means for creating a composite error by combining a plurality of rotation errors of the rotation error detection means, and a composite error of the memory output value of the memory output value creation means and the composite error creation means. and an operation management means for managing the operation timing of the second calculation means; The management means operates the second calculation means based on the timing signal of the operation timing generation means, and performs the operations of the first calculation means and the second calculation means substantially in parallel, thereby solving the above problem. This solves the problem.

According to the above-described configuration, the present invention divides the calculation from the detection operation by the speed detection means to the creation of the control signal by the control signal creation means 62 into the first calculation means and the second calculation means, By operating each in parallel while adjusting the timing, calculation time can be shortened.

Embodiment Hereinafter, a motor speed control device according to an embodiment of the present invention will be described with reference to the drawings, taking a capstan motor of a video tape recorder as an example. FIG. 2 shows a configuration diagram representing an embodiment of the present invention.

In Fig. 2, a DC motor 1 has a rotation sensor 2 and a load 1.
4 is directly rotationally driven. As the motor 1 rotates, the rotation sensor 2 generates an alternating current signal a Zq times per rotation (Zq is an integer greater than or equal to 4, here Zq-1000).
occurs. The AC signal a of the rotation sensor 2 is the speed detector 3
A digital signal corresponding to the period of the AC signal a is obtained.

A specific example of the configuration of the speed detector 3 is shown in FIG.

The AC signal a is waveform-shaped by a waveform shaping circuit 31 to obtain a shaped signal g. The shaped signal g is input to an AND circuit 33 and a flip-flop circuit 35. AND circuit 33
Further, the clock pulse p of the oscillation circuit 32 and the overflow output signal W of the counter circuit 34 are also input to the input side of the circuit. The oscillation circuit 32 is composed of a crystal oscillator, a frequency divider, etc., and generates a clock pulse p (approximately 500 kHz) that has a considerably higher frequency than the frequency of the alternating current signal a. The counter circuit 34 is a 12-bit up counter that counts up the contents every time the output pulse h of the AND circuit 33 arrives. Further, the overflow output signal W is "Ho" when the count content of the counter circuit 34 is less than a predetermined value, and when the count content of the counter circuit 34 exceeds a predetermined value, W changes to "L" (here, "HI+ (represents a high potential state, and "L" represents a low potential state).The data input type flip-flop circuit 35 uses the falling edge of the shaping signal g as a trigger signal to detect the "'H" input to the data input terminal. The output signal q is set to "H" (q=゛H゛). Moreover, when the reset signal r from the compensator 4 becomes "'H",
The internal states of the counter circuit 34 and the flip-flop circuit 35 are reset (b=”LLLLLLLLLLLL
L”, w-paH”, q=“L”).

Next, the operation of the speed detector 3 shown in FIG. 3 will be explained.

It is now assumed that the counter circuit 34 and the flip-flop circuit 35 have been reset by the reset signal r. When the AC signal a of the rotation sensor 2 changes from "L" to "Ho", the shaping signal g of the waveform shaping circuit 3 also changes from "L" to "II".
The clock pulse P of the oscillation circuit 32 is output as the output signal of the AND circuit 33.The counter circuit 34 counts the output signal of the AND circuit and changes its internal state (. Signal a changes from “H” to “
When it changes to “L”, the shaping signal g of the waveform shaping circuit 31 also changes to “H”.
The output signal of the AND circuit 33 becomes L, and the counter circuit 34 maintains its internal state.Furthermore, the flip-flop circuit 35 changes the data to "H" by the falling edge of the shaping signal g. ", and changes its output signal q from "L' to H'. The digital signal output from the counter circuit 34 is the rotation sensor 2.
The value is proportional to the period length (half period length) of the alternating current signal a, and is inversely proportional to the rotational speed of the motor l. A compensator 4, which will be described later, looks at the output signal q of the flip-flop circuit 35, and when q becomes "H", outputs a digital signal from the counter circuit 34, and then outputs a reset signal r to "H" for a predetermined short period of time. ", the counter circuit 34 and the flip-flop circuit 35 are reset to their initial states in preparation for the next speed detection operation. Note that when the rotation speed of the motor l is too slow, the alternating current signal a of the rotation sensor 2 is Because the cycle is long, the internal state of the counter circuit 34 becomes equal to or higher than a predetermined value, the overflow output signal W changes from high to I, and the output signal of the ant circuit 33 becomes "L", and the counter circuit 3
4 may hold a predetermined large value.

The compensator 4 shown in FIG.
, a ROM memory (ROM: read-only memory) 7 in which a plurality of predetermined programs and constants are stored, and a first program counter 8 , which indicates the execution address of a predetermined program stored in the ROM memory 7 . A second program counter 9, an interrupt vector 11 storing the start address of a predetermined interrupt program stored in the ROM memory 7, and an interrupt vector 11 that stores the contents of the second program counter 9 according to instructions within the program. The interrupt controller 10 and the D/A converter 12 constitute the interrupt controller 10 and the D/A converter 12.

The arithmetic unit 5 performs predetermined operations and calculations according to the instruction at the address in the ROM memory 7 indicated by the first program counter 8, and predetermined operations and calculations according to the instruction at the address in the ROM memory 7 indicated by the second program counter 9. Perform operations and calculations alternately. 1st
Program counter 8. Second program counter 9
When an instruction is executed, its contents are updated to indicate the address of the next instruction. By repeating such operations, two programs can essentially be executed in parallel.

The interrupt control unit 10 changes the contents of the second program counter 9 to the address of the interrupt vector 11 in response to an interrupt request instruction in the program, and starts execution of a predetermined interrupt program. Furthermore, when the processing of the predetermined interrupt program is completed, the second program counter 9
The contents return to the values before executing the predetermined interrupt program.

Therefore, when returning from the interrupt program, the second
The program executed by the program counter 9 resumes execution of the program that was being executed before the interrupt request instruction was executed. Regarding the programs executed by the second program counter 9, when an interrupt program is not executed, a program such as a system control program is executed. Furthermore, when the interrupt program is not being executed, the amount of calculation of the program executed by the second program counter 9 is:
It is assumed that the number of programs is considerably smaller than that of a capstan motor control program.

The compensator 4 calculates and processes the digital signal output from the speed detector 3 using a program to be described later, and outputs a control signal C. The control signal C output from the compensator 4 is input to the power amplifier 13, and the power amplified drive signal d(
A current proportional to the control signal c) is supplied to the motor 1.

Therefore, a speed control system is constituted by the motor l, the rotation sensor 2 (rotation sensor means), the speed detector 3 (speed detection means), the compensator 4 (compensation means), and the power amplifier 13 (driving means). The rotation speed is controlled to a predetermined value.

FIG. 1(A) shows a specific example of the first program executed by the first program counter 8.
B) shows a specific example of an interrupt program.

Next, the first program shown in FIG. 1(A) will be explained in detail.

[Step al] <Rotation error detection means>, arithmetic unit 5
inputs the output signal q of the flip-flop circuit 35 of the speed detector 3 and waits for the output signal q to become "H". That is, the speed detector 3 detects the cycle (half cycle) of the AC signal a and monitors the output of a new digital signal. When the output signal q becomes "H", the digital signal of the speed detector 3 is read and the speed detection value S (digital value) corresponding to the digital signal is changed, and the reset signal r is set to "H" for a predetermined period of time. The counter circuit 34 and flip-flop circuit 35 of the speed detector 3 are reset. Subtract the speed detection value S from a predetermined reference value S ref and multiply that value by R (here, R is a predetermined positive constant),
Calculate the current rotational error E of motor 1 [E=R・
(Sref-3) ].

[Step a2] <Control signal generation means> The memory output value Vo by the memory output value generation means to be described later and the current rotational error E are set at a predetermined ratio D:■ (here, D is OgD≦1
(Constant)) Arithmetic and synthesis are performed here to calculate the control signal value Y (Y=E−D・Vo). Control signal value Y to D/A converter 1
Two outputs are output and converted into a voltage (control signal) C corresponding to the control signal value Y.

[Step a3] - Operation timing creation means>
An interrupt request is issued to the interrupt control unit IO of the compensator 4.

The interrupt control unit 10 (operation management means) changes the contents of the second program counter 9 to the address of the interrupt vector 11 in which the start address of the interrupt program (described later) is set, and starts the interrupt program.

U step a4] <Mode discriminating means> The rotation speed, rotation direction, etc. of the capstan motor are set. If a change in rotational speed is requested, the predetermined reference value 5ref is changed to a desired value. Thereafter, the rotation error detection means returns to operation.

Next, the interrupt program shown in FIG. 1(B) will be explained in detail.

[Step b1] Storage of rotation error time series> The current rotation error E is stored and saved in a memory value F[11] corresponding to the first counter variable 11, which will be described later.
1] -E).

[Step b2] First counting means> Using Q (here, Q is an integer of 2 or more) as mod, count up the first count variable III every time a new speed detection value S is obtained. go. That is, I 1=11+1 (
I 1+1 to new L<Tl), then 11=Q
If so, reset 11 to O. If such an operation is performed, I1 will be an integer between O and (Q-1). Note that the initial value of 11 is O. If II is O (b3)
.

Execute operation (b4), if 11 is 1, execute operation (b5), if I1 is 2, execute operation (b6),
If I1 is not O, -1, 2, the interrupt program ends.

[Step b3] <Second counting means> Nx=L (Generally, Nx is an integer, and L is an integer of 4 or more.

Furthermore, since it is desirable that L be an integer multiple of (Zq/Q), such a case will be described below.

) as mod, (modulo), the first count variable 11
Every time becomes O (every time Q new speed detection values S are obtained)
, after counting up the second count variable 12, that is, after setting r2=T2+1, 12=Nx・L
If so, reset I2 to 0. If such an operation is performed, I2 will be an integer between 0 and Nx-L-1.

Note that the initial value of I2 is Nx-L-1.

[Step b4] Memory output value creation means> Integer J is I
2 (J-I2), Nx memory values M[J-nL (mod
Nx-L)] (n=1. ・=・.

Nx) is used to create a memory output value ■0 using the following equation.

Here, the value of the ratio Wn is 0 < Wn < 27Nx (n = 1, ”...
, Nx) (2), and is further standardized as Nx Σ Wn-11618,, C3) n·1. Specifically, Wn= l/Nx (n= 1.2.-, Nx)...
...C4) Then, by performing one division (or bit shift) after adding a predetermined dental memory value, the calculation in C1)2 can be easily realized. Note that this memory output value Vo is used in the control signal creation means and update storage means. This interrupt program then ends.

[Step 7 b5] <Synthetic error creation means> By the above-mentioned operation of saving the rotation error time series, F [m] (m=o
, 1. ..., Q-1) stores Q consecutive rotation errors. Among these, Fd (here, Fd is an integer greater than or equal to 2 and less than or equal to Q) latest rotation errors F CQ-m
] (m=1.2. ・-.

Fd) to a predetermined ratio Bm (m=1.2.
....

Fd) is added and synthesized to create a synthesis error Eg. That is, here, the coefficient Bm is Bm=BFd-m-+ (m=1..2...
, Fd)...(6) There is the following relationship. Saraotsuko, m=1 Otsuko is standardized.

This interrupt program then ends.

U step b6] <Update storage means> Compute and combine the memory output value vO by the memory output value creation means and the synthesis error Eg at a ratio of 1:1 to calculate an update value, which corresponds to the second count variable ■2. Update the memory value M[I2] in the RAM memory 6 that has been updated M[I2] -E
g+Vo), is stored until the next update. after that,
This interrupt program ends.

That is, in the compensator 4, a first operation (a first operation The second calculation means (second calculation means) realized by the rotation error detection means, the control signal generation means, and the operation timing generation means are executed in parallel while taking timing.

With this configuration, the second load 14 is extremely strong against a specific frequency of the load torque fluctuation that occurs (this is similar to the invention of the earlier application mentioned above.Furthermore, in this embodiment, There is a large amount of leeway in calculation time.
Let me explain in detail.

First, in the program executed by the first program counter 8, only the rotation error detection means, the control signal generation means, the operation timing generation means, and the mode discrimination means are operated, and the amount of calculation is very small. You can have a lot of leeway.

Further, the second program counter 9 normally executes a program such as system control. Interrupt programs execute interrupt programs by interrupting programs such as system control. Even if the rotational error storage means, the first counting means, the second counting means, the memory output value creation means, the composite error output creation means, and the updating means are operated, there is almost no influence on system control, etc.

Since the operations of the first program counter 8 and the second program counter 9 are performed in parallel, it is not necessary for the operation of the interrupt program by the second program counter 9 to be completed by the timing of the next rotation error detection means. The process can be completed by the timing of the next control signal generating means, and even in the program executed by the second program counter 9, a very large margin of computation time can be obtained.

As described above, since a large amount of calculation margin is obtained for the calculations executed by the first program counter 8 and the second program counter 9, motor control is possible even if the detection period detected by the speed detector 3 is shortened. becomes. When the detection period of the speed detector 3 becomes shorter, the motor control performance is improved for higher frequency components of load torque fluctuation, and the motor control performance is also greatly improved for lower frequency components.

In this way, a large margin of computation time can be obtained by
This is a huge advantage for motor control performance. By improving the control performance of the motor, it is possible to suppress fluctuations in motor rotation due to fluctuations in load torque.

Furthermore, when this embodiment is used in the capstan motor of an actual video tape recorder, new processing such as a low-frequency performance improvement filter and control stability determination will be required for the first program counter 8. As described above, if the second program counter 9 has sufficient calculation time, operations including these processes can be realized.

In the above-mentioned embodiment, in the first operation and the second operation, the arithmetic unit 5 (operation execution means), ROM memory 7 (instruction storage means), and RAM memory 6 (digital value storage means) are substantially I'm sharing this. This not only significantly reduces costs, but also greatly simplifies the exchange of digital values between the first operation and the second operation by passing them or using a common RAM memory.

Note that in the first program, an interrupt request instruction is used, the state of a specific variable is changed at the timing of executing the interrupt request instruction, and the state of the specific variable is changed in the program executed by the second program counter 9. By programming to detect changes in variables, parallel processing can be performed at almost the same timing as in the previous embodiment. If this is done, the program executed by the second program counter 9 would be subject to considerable restrictions, which would be impractical. However, if the amount of calculation of the program executed by the second program counter 9 is very small when the interrupt program is not being executed, the interrupt control section 10 becomes unnecessary and is therefore very effective.

FIG. 4 shows an example of an interrupt program for the compensator 4, which takes into consideration the stability of the entire control system. Here, the method of preparing the memory output value in the memory output value creation means and the way of using the memory output value of the memory output value creation section in the control signal creation means are improved. Note that the overall configuration is the same as that shown in FIG. 2, and a description thereof will be omitted. Further, the first program executed by the first program counter 8 is the same as that in FIG. 1, and the explanation thereof will be omitted. Furthermore, when the second program counter 9 indicates that no interrupt program is being executed, a program such as system control is being executed.

Next, the interrupt program shown in FIG. 4 will be explained in detail.

[Step bli] <Saving rotation error time series> Memory value F[11] corresponding to the first counter variable 11 described later
The current rotation error E is stored and saved ((F[11
Ko=E).

[Step b12] <First counting means> Modify Q
(method), the first count variable 11 is counted up every time a new speed detection value S is obtained. Tl or Q
When it becomes equal to a (here, Qa is an integer smaller than Q), change the memory output value ■0 to V[PXE, which will be described later, and [
1 or Qa! If these values are not equal, such a change operation is not performed. As a result, in the range 11<Qa, Vo-V
[Px -13 (described later), and in the range of 11≧Qa, Vo=V'Px3b.Furthermore, 11 becomes O
If so, execute the operations (b13) and (b14) and
If Tl is 1, operation (b15) is executed, if 11 is 2, operation (b16) is executed, and if Tl is not 0.1.2, the interrupt program ends.

[Step b13] <Second counting means> With Nx-L as mod, a second count is performed every time the first count variable 11 becomes 0 (every time Q new speed detection values S are obtained). After counting up the variable 12 and determining how many times it is [Step b14] <Memory output value creation means> After sequentially transferring the contents of the register variable X [m+1] to X [m] (m=o, 1, 2, . . .・.

2Kd-1), Nx-L as mad, the second count variable ■2 is Px4-Kd (here, Px is 1 or more and 3
The integer i that is the sum of the following integers, Kd is an integer greater than or equal to 1)
Calculate J [J= 12+Px+Kd(mod N
x・L)]. Memory value in RAM memory 6 BMCJ-n
L (mod Nv ・L) (n=1
．． -----.

Nx ), the calculated value calculated by the following formula is
Put it in 2Kdl.

・・・・・・(8) Here, the value of Wn is (2), '(3) formula and (4
) meets 2. That is, from X [2Kd]
(2Kd+l) consecutive calculated values (calculated values obtained from Nv memory values separated by L intervals) are obtained. Next, change the contents of the register variable V[m±1] to ■[m
'] after sequentially transferring to (m-0+1,...).

Px-1'), X [m] (m=o, 1.
..., 2Kd) Predetermined ratio Cm (m=o, L
.=., 2Kd) to obtain the latest memory output value and put it into 3Px].

shall be. Here, the ratio CITI! This has the following relationship.

Cm=02. ,-, (m=0.1.2.-,
(P
x+1) memory output values are obtained. At this time, let Jl be the integer J in equation (9) when practically calculating V IPx ], and (9
) If the integer J in the formula is J2, then there is a relationship of J1=J2+Px. That is, there is a difference between V[Px] and ]total 0] corresponding to the integer Pxl. Next, the memory output value VO used in the control signal generation means is set to V[:P
x-1] (Vo = V[Px-1]). after that,
This interrupt program ends.

[Step b15] <Synthetic error creation means> By the above-mentioned operation of saving the rotation error time series, F [m] (m=o
, l . . . -, Q-1), Q consecutive rotation errors are stored. Among these, Fd latest rotation errors F (Q-m3 (m=1゜2..., Fd
) to each predetermined ratio Bm (m, = 1.2...
, Fd) are added and synthesized, and the synthesis error Eg
create. [C5), C6L (Riki Ni]. After that,
This interrupt program ends.

[Step b16] <Update storage means> An update value is calculated by calculating and combining the old memory output value ■[0] created by the memory output value creation means and the synthesis error Eg at a ratio of 1:1, and the second The memory value M[I2] in the ram memory 7 corresponding to the count variable I2 of M is updated.
[12]=Eg±V[0]L Stored until the next update. This interrupt program then ends.

As in this embodiment, an operation for taking a weighted average may be inserted into the memory output generation means, or the first memory output value Vo (
V[Px] and the second memory output value v[o2 of the memory output value creation means used in the update storage means. ), it is possible to obtain good control characteristics within the control range and to stabilize the operation of the entire control system. , admitted.

Further, in this embodiment, the timings of the operation of the memory output generation means, the operation of the composite error generation means, and the operation of the update storage means are shifted with respect to the detection operation of the speed detector 3. As a result, the amount of calculation required within one detection period of the speed detector 3 is significantly reduced, and it is also possible to use a microcomputer with a slow operating speed for the compensator 4.

In particular, as shown in this embodiment, when the operation of the memory output generation means, the operation of the synthetic error generation means, and the operation of the update storage means include many transfers and multiplications, The amount of calculation required within a period is reduced.

Furthermore, when the amount of calculation of the interrupt program executed by the second program counter 9 decreases, the calculation time that can be used by programs other than the interrupt program increases. Therefore, there are very few restrictions on the program when performing other motor control or system control.

It should be noted that calculations using the ratios Wn and Cm are not limited to the above-mentioned formats, but may be of any type as long as they realize the contents of the program described above, and it goes without saying that various equivalent modifications are possible.

In addition, in each of the above-mentioned embodiments, only the rotational speed of the motor is detected by the speed detector, but in addition to this, the rotational phase of the motor is detected by a well-known phase detector, and the two are combined to rotate the motor. It goes without saying that the error is included in the present invention.Also, the output of the compensator may be converted into a digital signal or a PWM signal (pulse width modulation signal),
The output signal of the power amplifier may be a PWM signal. Further, a brushless DC motor may be used as the motor.

Furthermore, the compensator can be configured completely in hardware,
It may be possible to cause the program to perform the same operations as those performed by the program B described above. In addition, various changes can be made without changing the gist of the present invention.

Effects of the Invention The motor speed control device of the present invention requires less calculation time.
It has extremely good characteristics at a specific frequency, and rotational speed fluctuations due to load torque fluctuations are greatly reduced. Therefore, if the capstan morph of a video tape recorder is constructed based on the present invention, the running speed of the magnetic tape can be controlled extremely accurately, and a high-performance video tape recorder with less wow and flutter can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a flow chart showing an example of a built-in program of a compensator of a motor speed control device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the overall structure of the embodiment of the present invention.
FIG. 3 is a configuration diagram showing a specific example of the configuration of the speed detector shown in FIG. 2, and FIG. 4 shows an example of a built-in program of a compensator of a motor speed control device representing another embodiment of the present invention. It is a flowchart. 1... Motor, 2... Rotation sensor, 3
...speed detector, 4...compensator,
... Arithmetic unit, 6...-- Ram memory, 7...
...ROM memory, 8...-first program counter, 9...second program counter, 1
0...υj interrupt control unit, 11...Interrupt vector, 12...--D/A converter, 13
-...Power amplifier, 14...Load. Name of agent: Patent attorney Akira Okaji and two others Figure 1 <A) Figure 3

Claims (4)

[Claims] (1) rotation sensor means for generating an alternating current signal with a period corresponding to the rotational speed of the motor; speed detection means for detecting a plurality of times per rotation of the motor based on the alternating current signal of the rotation sensor means; and a first calculation. compensating means for generating a control signal using means and a second calculating means, and driving means for driving the motor according to the control signal of the compensating means, and the first calculating means is configured to detect the speed of the speed detecting means. a rotational error detection means for obtaining a rotational error according to a signal; a control signal generation means for generating the control signal by calculating and combining a memory output value and the rotational error of the rotational error detection means; and a timing of the second calculation means. an operation timing generation means for generating a signal; a memory output value generating means for generating the memory output value by combining a plurality of rotational errors of the rotational error detecting means; managing the operation timing of the update storage means for updating and storing the memory values of the memory means substantially sequentially, and the second calculation means, using an update value corresponding to the value obtained by calculating and combining the synthesis errors of the synthesis error creation means; and an operation management means for controlling the operation of the second calculation means based on the timing signal of the operation timing generation means, and controlling the operation of the first calculation means and the operation of the second calculation means. A motor speed control device characterized in that operations are performed substantially in parallel. (2) The motor speed control device according to claim (1), wherein the operation management means of the second calculation means always monitors the timing signal of the operation timing generation means of the first calculation means. . (3) The operation of the first arithmetic means includes a first instruction storage means in which a series of arithmetic operations are stored in advance, a first digital value storage means in which a plurality of digital values are stored, and the first a first address generation means for generating an address of the instruction storage means; and a first operation execution means for operating the first operation means in accordance with the instructions stored in the first instruction storage means. , the operation of the second arithmetic means is performed by a second instruction storage means in which a series of arithmetic operations is stored in advance;
a second digital value storage means storing a plurality of digital values; and a second digital value storage means for generating an address of the second instruction storage means.
and a second operation execution means for operating the second operation means in accordance with the instructions stored in the second instruction storage means, and generates the operation timing of the first operation means. The operation management means of the second calculation means changes the contents of the second address generation means of the second calculation means to a preset address in accordance with a timing signal of the second calculation means. Claim (1) characterized in that the operation of the calculation means is performed.
) Speed control device for the motor described. (4) In the first calculation means and the second calculation means, the first
At least one set of the instruction storage means and second instruction storage means, the first digital value storage means and second digital value storage means, and the first operation execution means and second operation execution means is shared. The motor speed control device according to claim 3, characterized in that: