JPS6289488A - Speed controller for motor - Google Patents

Abstract

PURPOSE:To prevent a motor from varying at its speed by reducing frequency transfer function from the variation in a load torque to the variation in the rotating speed of a motor in a specific frequency. CONSTITUTION:A speed detector 3 outputs a digital signal (b) in response to the period of an AC signal (a) output from a rotary sensor 2. A compensator 4 compares a speed detection value S corresponding to the signal (b) with a reference value Sref to obtain a rotary error E multiplied by R of gain. A calculated value V and the error E are added at a ratio of D:1 to obtain a control signal Y. The value V and the error E are added at a ratio of 1:1 to obtain an updated value and updated and stored as a new digital value M(I). Further, next new combined value V is obtained from the digital value group in a ram range.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a motor speed control device. Conventional technology A motor speed control device that detects the rotational speed of a motor using a speed detector and controls the power supplied to the motor based on the detection signal is widely used in cab stan motors of video tape recorders, cylinder motors, etc. (For example, see Japanese Patent Application No. 56-142724 proposed by the present applicant). However, such a speed control device only performs conventionally used proportional, integral, and differential control, and cannot sufficiently suppress fluctuations in rotational speed due to fluctuations in load torque. This will be explained below with reference to the drawings. The configuration of a conventional motor speed control device is shown in FIG. A rotation sensor 2 directly connected to the DC motor 1 generates an AC signal as the motor 1 rotates. The speed detector 3 generates a DC-like voltage according to the period of the AC signal from the rotation sensor 2, and inputs it to the proportional compensator 9. The signal amplified by a predetermined factor by the proportional compensator 9 is input to the power amplifier 8 . The power amplifier 8 amplifies the power of the input signal to supply power to the motor, increases or decreases the torque generated by the motor 1, and controls the rotational speed of the load 10. Problems to be Solved by the Invention A control block diagram of this conventional speed control device is shown in FIG. In Fig. 9, the value (Tm - TI) obtained by subtracting the load l and the torque T1 from the generated torque Tm of the motor 1 becomes the net driving torque (addition point 41), and the combined moment of inertia Jm of the motor 1 and the load 10 is Drive rotation. The drive torque is integrated by the moment of inertia Jm (block 42)
, is converted into the rotational speed ωm of the motor 1. Note that S in block 42 is a Laplace operator. After the rotational speed ωm is multiplied by KV and detected by the rotational sensor 2 and the speed detector 3 (block 43), it is compared with the reference signal 5ref (addition point 44) to obtain an equivalent speed error e. The speed error e is amplified by R times by the proportional compensator 9 (block 45), further converted into a current by Ba times by the power amplifier 8 (block 46), and supplied to the motor 1. The motor 1 has a torque constant Kt of the supply current of the power amplifier 8.
Generating double the torque Tm (block 47) The transfer function from the load torque TI to the rotational speed ωm is ω m G(s)=−1+(KvRBaKt)/[Jm s). A Bode gain diagram of the frequency transfer function G(jω) is shown in FIG. Within the control range below the corner frequency fc, G (jω)#-1/ (KvRBaKt) -(2
) can be approximated as (2) If the gain R of the proportional compensator 9 is made larger than the second one,
It can be seen that fluctuations in the rotational speed ωm of the motor 1 due to fluctuations in the load torque TI are reduced. However, in practice, the speed detection operations of the rotation sensor 2 and the speed detector 3 have a time delay, so if the gain R of the proportional compensator 9 is made too large, the control system becomes unstable. . That is, there is a limit to the gain R of the proportional compensator 9. As a result, the rotational speed of the motor 1 fluctuated greatly due to torque fluctuations caused by the load 10. In consideration of these points, the present invention has been devised to significantly reduce fluctuations in the rotational speed of the motor due to fluctuations in load torque. Means for Solving the Problems The present invention includes a rotation sensor that generates an alternating current signal with a period corresponding to the rotational speed of a motor, and a digital signal corresponding to the period of the alternating current signal of the rotation sensor at Zq per rotation of the motor. speed detecting means for calculating and storing a control signal based on the digital signal of the speed detecting means; power amplifying means for supplying the motor with a corresponding electric power; A counting operation is performed in response to obtaining a new digital signal, and Nx-L (where Nx is a positive number of 1 or more, and L is 4
a counting means for generating a count value (modulo) of an integer above), and at least NxL digital values M in a sequentially rewritable RAM area.

[0] to M[Nx
L-1), and at least Nx digital values M [J
-nL (modNxL)) (n=1.
. The digital values of the memory means corresponding to the count value I of the counting means are sequentially changed to M (0) and M (1) by update values corresponding to the values I of the count means. M (2) The update storage means updates and saves in the order of .
control signal generating means for producing the control signal by adding and combining at a ratio of 1, and the ratio is 0.25.
The above problem is solved by satisfying ≦D≦0.5. In the present invention, by adopting the above-mentioned configuration, the frequency transfer function from load torque fluctuation to rotational speed fluctuation becomes O or extremely small at a specific frequency, and at other frequencies, the characteristics are almost the same as the conventional characteristics. It turns out that it becomes. That is, the influence of fluctuations in a specific frequency of load torque was significantly reduced, and the effect of suppressing fluctuations in other frequencies as well as that of the conventional technology could be obtained. As a result, the composite value of rotational speed fluctuations was significantly reduced, and a high-performance motor speed control device was realized. Embodiment FIG. 2 shows a configuration diagram representing an embodiment of the present invention. In Fig. 2, a DC motor 1 has a rotation sensor 2 and a load 1.
0 is directly rotationally driven. The rotation sensor 2 rotates Zq times per rotation as the motor 1 rotates (Zq is an integer of 4 or more; in the capstan motor of a video tape recorder,
Normally, an AC signal a of Zq=100> is generated. The alternating current signal a of the rotation sensor 2 is input to the speed detector 3, and a digital signal corresponding to the period of the alternating current signal a is obtained. A specific example of the configuration of the speed detector 3 is shown in FIG. The AC signal a is waveform-shaped by a waveform shaping circuit 31,
A shaped signal g is obtained. The shaped signal g is input to an AND circuit 33 and a flip-flop 35. AND circuit 3
Further, the clock pulse p of the oscillation circuit 32 and the overflow output signal W of the counter 34 are also input to the input side of the counter 3. The oscillation circuit 32 is composed of a crystal oscillator, a frequency divider, etc., and generates a clock pulse II) (approximately 500 kHz) that has a considerably higher frequency than the frequency of the shaped signal g. The counter 34 receives the output pulse h of the AND circuit 33
12 vias that count up the contents each time they arrive 1
・It is an up counter. Further, the overflow output signal W is "H" when the contents of the counter 34 are below a predetermined value, and changes to "L" when the count contents of the counter 34 exceed the predetermined value. (Here, "H" represents a high potential state, and "■" and "'" represent a low potential state.) The data input type flip-flop 35 inputs data using the falling edge of the shaping signal g as a trigger signal. The "H" input to the terminal is taken in and the output Q is set to "H"(q-"H").In addition, the reset signal r from the compensator 4 is
When becomes H”, the counter 34 and the flip-flop 35
The internal state of is set (b-”L L L L
L L L L L L LL"1 W-H", q-"
Next, the operation of the speed detector 3 shown in FIG. 3 will be explained. It is assumed that the counter 34 and the flip-flop 35 are reset by the reset signal r. When changes from “L” to “H”,
The clock pulse p of the oscillation circuit 32 is output as the output signal of the AND circuit 33. The output signal of the counter 34 is counted and its internal state is changed. When the output signal g of the waveform shaping circuit 31 changes from "■(" to "I4", the output signal g of the AND circuit 33 becomes "I2",
Counter 34 maintains its internal state. Also, data “11” is read in by the falling edge of the flip-flop,
The output signal q is changed from 1,゛ to "I". The digital signal S of the counter 34 has a value proportional to the (half) period length of the AC signal a of the rotation sensor 2, and is inversely proportional to the rotation speed of the motor 1. A compensator 4, which will be described later, receives the output signal q of the flip-flop 35.
When q becomes I]'', input the digital signal of the counter 34, and then set the reset signal r to ``H'' for a predetermined short time to reset the counter 34 and the flip-flop 35 to the initial state. However, when the rotational speed of the motor 1 is too slow, the internal state of the counter 34 exceeds a predetermined value because the period of the output signal 8 of the waveform shaping circuit 31 is long. The overflow output signal W changes from "■4" to "■,", the output signal of the AND circuit 33 becomes "■,", and the counter 34
may hold a predetermined large value. The compensator 4 shown in FIG. 2 is composed of an arithmetic unit 5, a memory 6, and a D/A converter 7. The compensator 4 in FIG.
Output. The control signal C of the compensator 4 is input to the power amplifier 8, and the power amplified drive signal d (current proportional to the control signal C) is supplied to the motor 1. Therefore, a speed control system is constituted by the motor 1, the rotation sensor 2, the speed detector 3, the compensator 4, and the power amplifier 8, and the rotation speed of the motor is controlled to a predetermined value. The memory 6 of the compensator 4 is divided into a ROM area (ROM: read-only memory) in which predetermined programs and constants are stored, and a RAM area (RAM: random access memory) in which necessary values are stored. The arithmetic unit 5 performs predetermined operations and calculations according to a program in the ROM area. 1st
The figure shows a specific example of the program. Next, the operation will be explained in detail. (1) First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3, and waits for the signal q to become "H". At the same time, the speed detector 3 detects the (half) cycle of the AC signal a and monitors the output of a new digital signal. (2) When q becomes "I", read the digital signal of the speed detector 3, convert it to the speed detection value S (digital value) corresponding to the digital signal, and set the reset signal r to "I" for a predetermined period of time. ]” to reset the counter 34 of the speed detector 3 and the flip-flop 7 35. (3) Subtract the detected speed value S from the predetermined reference value S ref (Eo = Sref S) to obtain the value E. is multiplied by R (E=R·Eo), and the current rotation error E of the motor 1 is calculated (rotation error detection means). (4,1Nx -L (here, Nx is an integer of 1 or more, and L is an integer that is an integer of 2 or more than Zq) as a modulus, and the variable I is set every time a new speed detection value S is obtained. Count up (counting means). That is, L
I+], (make I+1 a new I), then I=
If Nxl, then set I=0. If such an operation is performed, ■ becomes an integer between O and Nx, L-1. Note that the initial value of ■ is N x L −1. (5) A calculated value V by a calculated value calculating means, which will be described later, and a current rotational error E are added and combined at a predetermined ratio D: to calculate a control signal value Y (control signal generating means). Zunawachi,
Y=E+D・■. Here, the ratio is 0.25≦D≦0.
A value within the range of 5 is selected. (6) Output the control signal value Y to the D/A converter 7 and convert it into a DC voltage (control voltage) corresponding to the value of Y. (7) Calculate an updated value by adding and combining the calculated value ■ by the calculated value calculating means (to be described later) and the current rotational error E at a ratio of 1:1, and Update the digital value M [1] M CI) = E
+V), is stored and saved until the next update (update storage means). (Calculate the integer J by adding 1 to ■, with 81NxL as mo and d, J = I + 1. (mod, NxL))],
Nx digital values M [J-nL (mod, Nxl,) ) (
Using n=1, . (mod N x L) ) --(3)
Here, the value of the ratio Wn is 0<Wn<2/Nx (n=1.----, Nx)
= (41x Σ W n, = ] ・
...(5) Assume that n=1 is not satisfied. Specifically, Wn=1/Nx (n=1.----, Nx) =・
(If the value is set to 61, favorable characteristics are easily obtained. This calculated value V is calculated after the next speed detection value S is obtained and the counting means increments the current value I (substantially I and J are This is used in the control signal generation means and the update storage means.If configured in this way, it is extremely resistant to fluctuations in the load 1-lux caused by the load 10 in FIG. A control block diagram of this embodiment is shown in FIG. 4. The same elements as those shown in FIG. The operation corresponds to the broken line portion 50 in the figure.The reference value 5ref and the detected value S are compared at the addition point 44, and the rotation error E is obtained by multiplying the gain by 2.
(block 45). The calculated value ■ and the rotational error E are added and combined at a ratio of D:1 to obtain a control signal value Y (addition point 53 and block 54). Further, the calculated value ■ and the rotation error E are added and combined at a ratio of 1:1 to obtain an updated value, which is updated and stored as a new digital value M (1) (addition point 51). Furthermore, from the group of digital values in the RAM area, (3
Since the next new calculated value V is calculated according to the formula ), the relationship between the digital value MCI) and the calculated value V is shown in block 52.
It is expressed as follows. Here, 2 in block 52 is z=
exp (sTx) - (71, where Tx corresponds to one sampling period of the speed detector 3. From the load torque TI of the control block in FIG. 4, the rotational speed ω
Calculating the transfer function to m, Qx (s) = 1 + (KvRBaKt)/[Jm s ・H
(s)) n=1. Within the control range below the corner frequency fc, Gx (jω)# (1/ (KvRBaKt
))・H(jω) #G(jω)・H(jω)...α0) GO) formula is the control characteristic Gx (jω) of this embodiment
This means that is equal to the conventional control characteristic G[Jω) multiplied by H(jω). In FIG. 5, Nx=2. W1=0.5. An example of the amplitude characteristic of the frequency transfer function H(jω) in the case of W2-〇, 5 is shown. ■ in Figure 5 is for D=0.5, and ■ is for D=0.25.
For comparison, the case where D=1 is shown in (■). Also, fr is f r = 1/ (L-Tx) -Q
υ, and H(jω) is a periodic function of fr. As shown in ■ and ■ in Figure 5, the frequencies fr and 2fr
, 3fr, ......, the frequency transfer function is N(
It can be seen that (jω) is 1-0. And, as can be understood by comparing ■, ■ and ■, D=
1 (■), when D=0.5 (■) and when D=0.25 (■), fr, 2fr,...
It was found that 111(jω)1 is approximately equal to 1 also at frequencies other than . Generally, the smaller D is, the more fr. IH(jω
) 1 approaches 1. However, if D is made small, fr, 2fr, ......IH(jω) in the vicinity
It was also found that the frequency range where l<<1 becomes narrower. That is, there is an optimal range for the ratio value, and if 0.25≦D≦0°5 as in this embodiment, the frequency transfer function Gx (jω) will be the frequencies fr, 2fr. 3fr, . . . and its neighboring frequencies, IGx(jω)1=0 and 1Gx(3ω)l<<1, and at other frequencies, the conventional frequency transfer function G(jω) almost equal. As a result, a very good control characteristic Gx (jω) can be obtained, and the composite value of the fluctuations in the rotational speed ωm of the motor 1 due to the fluctuations in the load torque TI can be reliably made smaller than the conventional control performance value. It has become possible. It was also found that such an effect is more easily obtained as Nx is larger. However, in order to reduce the number of memories in the RAM area while obtaining the above-mentioned effects, it can be said that Nx=2 is preferable. Also, if L is made equal to an integer multiple of 2 or more of Zq, then (
If L is set to a value corresponding to an integer multiple of 2 or more of one rotation period of the motor 1), there is an effect of greatly suppressing fluctuations in the rotational speed ωm due to fluctuations in the load torque T1 as a whole. Next, this will be explained using the capstan motor of a video tape recorder as an example. Since the load on the capstan motor is a magnetic tape or a pinch roller, the load fluctuation caused by the load 10 is a component that is synchronized with the rotation of the motor 1 (
(Periodic load fluctuations with one rotation of motor 1 as the basic cycle)
In addition, load fluctuation components with a frequency lower than the rotational frequency of the motor 1 often occur. Such load fluctuations cause fluctuations in the rotational speed of the capstan motor, causing wow and flutter in the tape speed. By the way, such load fluctuations are often periodic fluctuations that have a period that is an integral multiple of the period of one rotation of the motor 1, and conventional fluctuations in the rotational speed of the motor 1 also have a period that is an integral multiple of the period of one rotation. It was found that many periodic fluctuations occur in low frequencies. Therefore, if L is set to a value corresponding to an integer multiple of 2 or more of one rotation period of motor 1, then fr will be an integer multiple of 2 or more of the rotation frequency fm of motor 1, and the load l - torque T1 It is possible to effectively reduce the change in the low frequency of the motor 1 by 1 minute. Such an effect can be obtained by increasing the gain of the proportional compensator 9 of the conventional motor speed control device shown in FIG.
This cannot be obtained by adding an integral or differential compensator after . It should be noted that the larger the value of L, the more effective it is against long-cycle load fluctuations, but the size of the ram area becomes larger, so there is a limit in practice. Normally, it is preferable to set L to six times the period of one rotation of the motor from the following point of view. Zunawachi,
Since 6 has many divisors such as 1.2 and 3.6, it completely suppresses fluctuations in rotational speed due to load fluctuations with periods that are 1.2 and 3.6 times the period of one rotation of motor 1. We can expect that. FIG. 6 shows an example of a program for the compensator 4 that takes into consideration the stability of the entire control system. Here, improvements have been made in the method of calculating update values in the update storage means, the number of calculated values prepared in the calculated value calculating means, and the way in which the calculated values of the calculated value calculating means are used in the control signal generating means. Next, its operation will be explained in detail (the overall configuration is the same as that in FIG. 2, so the explanation will be omitted). Ql) First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3, and waits for the signal q to become "H". That is, the speed detector 3 detects a (half) cycle of the AC signal a and monitors the output of a new digital signal. (b) When q becomes "H", the digital signal S of the speed detector 3 is read, the speed detection value S (digital value) corresponding to the digital signal S is restored, and the reset signal r is kept "H" for a predetermined period of time. counter 3 of speed detector 3
4 and reset the flip-flop 35. 0■ Subtract the speed detection value S from the predetermined reference 4fiSref (Eo-8ref-8), multiply JlaEo by R times E=R-go), and calculate the current rotational error E of motor 1 (rotation error detection means). Q4) Set Nx-L as mod, and count up the variable I every time a new speed detection value S is obtained (
counting means). The latest calculated value V (CPx) calculated by the calculated value calculation means described later and the current rotational error E are added and synthesized at a ratio of D:1 (0.25≦D≦0.5), and the control signal value is Calculate Y (control signal generation means). That is, Y
=E+D−V CPx). Q61 Outputs the control signal value Y to the D/A converter 7,
Converts to a DC voltage (control signal) corresponding to the value of . 0 power Old calculated value calculated by the calculated value calculation means described later ■

[0] and the current rotational error E are added and combined at a ratio of ]:1 to find the added value MO (MO=E+V (
0) ), Nx L as m o d, count variable I to Qf (Qf is an integer greater than or equal to 2, Qf=
(preferably 3) minus the integer K (K-1-Q
f (mod NxL)]. Transfer the contents of register variable) ((m+1.) to X Cm) in order. m=0.1, 2. −． 2Qf-1),X
Insert MO into [2Qf). That is, X (2Qf)
From X

2 Q f -1-1 consecutive addition values to [0] (addition values obtained by adding and combining the calculated value and the rotation error at a ratio of 1=1) are obtained. Next, a predetermined positive ratio C to X (m)
A new update value is obtained by adding and combining the values multiplied by m (m=o, 1. . . . = 2Qf), and is stored and saved as a digital value M (K) in the RAM area until the next update (update storage means ). Here, the ratio Cm has the following relationship. Cm=C2Cm=C2Qf-,1,=・,Qf)-02
)08) Set NxL as mod to count variable 1 to l-1
-Px (Px is an integer greater than or equal to 1 and less than or equal to 5, Px=3
(preferably)) [J=T+1+
Px (mod NxL)), register variable V(m-
1-1] to V(m) in order, then (m=
0.1. =-, Px-1), dicicle value group M [J-nL (mod NxL)) in the RAM region (n=1.
--, Nx) and enter the latest calculated value calculated by the following formula into VCPx) (calculated value calculation means). After that, the operation returns to 0υ. Nx n=1 (nod NxL))=J4) Here, the value of Wn satisfies equations (4), (5), and (6). That is, from V= CPx)

[0]
Obtain consecutive Px+1 calculated values. At this time, V(
When calculating Px), let the integer J in the formula 04) be Jl,
■

If the integer J in the opening formula when calculating [0] is J2, then there is a relationship of J1=J2+Px. In other words, V(Px) and ■

There is a gap between [0] corresponding to the integer Px. As already explained, after obtaining the next speed detection value S and incrementing the count value I of the counting means, VCPx) is used in the control signal generating means, and

[0] is used in the update storage means. As in this embodiment, the first calculation value of the calculation means and the calculation used in the update storage means are used for inserting a calculation for taking a weighted average into the update storage means, or for the control signal generation means. If a predetermined deviation is provided between the near calculated values of the value calculation means, it is necessary to confirm that not only the above-mentioned good control characteristics can be obtained within the control range, but also the operation of the entire control system will be stable. satisfies the Nyquist stability condition). In particular, in order to simplify calculations while ensuring the stability of the control system, Qf=3, Px
=3. I also learned that it is better to set L>Qf0Px. FIG. 7 shows another example of a program for the compensator 4 that takes into consideration the stability of the entire control system. Here, the method of calculating the calculated value in the calculated value calculating means and the number of preparations, and the way of using the calculated value of the calculated value calculating means in the control signal generating means are improved. Next, its operation will be explained in detail (the overall configuration is the same as that in FIG. 2, so the explanation will be omitted). (21) First, the arithmetic unit 5 inputs the output signal q of the flip-flop 35 of the speed detector 3, and waits for the signal q to become "H". That is, the speed detector 3 detects a (half) cycle of the AC signal a and monitors the output of a new digital signal. B (22) When q becomes "H", read the digital signal S of the speed detector 3, change it to the speed detector S (digital value) corresponding to the digital signal S, and set the reset signal 1 to r for a predetermined time. The counter 34 and flip-flop 35 of the speed detector 3 are reset to "H". (23) Subtract the detected speed value S from the predetermined reference value 5ref (EO=Sref S), multiply that value E0 by R (E=R-Eo), and calculate the current rotational error E of the motor 1 ( rotation error detection means). (24) Using Nx-L as rnod (modulus), count up the variable ■ every time a new speed detection value S is obtained (counting means). (25) The latest calculated value V(Px) calculated by the calculated value calculation means described later and the current rotation error E)! c.
D: Additive synthesis at a ratio of 1, 0.25≦D≦0.
5) Calculate the control signal value Y (control signal generation means). That is, Y=E+D −V (P x). (26) Output the control signal value Y to the D/A converter 7 and convert it into a DC voltage (control signal) corresponding to the value of Y. (27) Old calculated value v calculated by the calculated value calculation means described later

[0] and the current rotational error E are added and combined at a ratio of 1:1 to calculate an updated value, and the digital value MC in the ram area corresponding to the count value I of the counting means is calculated.
I] to update M(1)-E1V

[0]), is stored and saved until the next update (update storage means). (28) Calculate the integer J by adding 1+px+Qf (Px is an integer greater than or equal to 1 and less than or equal to 5, and Qf is an integer greater than or equal to 2) to the count variable I with N x L as mod [J=1+1→- Px → −Qx, (mod NxL)
). Transfer the contents of register variable X(m+1) to X Cm) in order, m=o, 1.2. −. 2Qf-1), the sum of the Nx digital value group M [J-nL (m, od NxL)) (n=1゜..., Nx> in the RAM area) is calculated by the following formula. Enter into 2Qf) to X

2Qf+1 added values (added values obtained from Nx digital values) consecutive to [0] are obtained. Next, register variable V(
After sequentially transferring the contents of m+1) to V (m),
=0.1. -, Px-1). X Cm) (m=0.1.-.2Qf), the latest calculated value is obtained by adding and combining the multiplied values, and is input into V(Px) (calculated value calculation means). That is, from V(Px) to V[0
], we have obtained px+1 consecutive calculated values. Here,
The ratio Cm has the relationship of Q2), formula 09. After that,
The operation returns to (21). At this time, the integer J in formula 051 when calculating V(Px) is set to Jl, and the actual V(Px) is

If the integer J in the α0 formula when calculating [0] is J2, then J1=J2+Px
There is a relationship between That is, VCPx) and V

There is a gap between [0] corresponding to the integer Px. As already explained, after obtaining a new speed detection value S and incrementing the count value I of the counting means, V(Px) is used in the control signal generating means, and

[0] is used in the update storage means. As in this embodiment, an operation for taking a weighted average and an operation for preparing a plurality of calculated values are inserted into the calculated value calculation means, and updated with the first calculated value of the calculated value calculation means used in the control signal generation means. If a predetermined deviation is provided between the second calculated value of the calculated value calculation means used in the storage means, good control characteristics as described above can be obtained, and the operation of the entire control system will also be stabilized (Nyquist ). In this case as well, in order to simplify the calculation while ensuring the stability of the control system, Qf=3. Px=3゜L>Qf+Px
It is better to make it . It should be noted that calculations using the ratios Wn and Cm are not limited to the above-mentioned forms, but may be any form that realizes the contents of the above-mentioned program, and it goes without saying that various equivalent expression transformations are possible. Further, when a new rotation error is obtained, the control signal generation means first outputs a new control signal, and then the calculated value calculation means calculates the calculated value to be used at the next sampling point. If so, the calculation time of the calculated value calculation means can be lengthened, and the time delay until the control signal is output can be shortened.
It is easy to ensure the stability of the control system. In each of the above-mentioned embodiments, only the rotational speed of the motor is detected by the speed detector, but in addition to this, the rotational phase of the motor is also detected by a well-known phase detector, and both are combined and detected as a rotational error. Needless to say, these are included in the present invention. It is also possible to convert the output of a compensator into a digital signal or PWM signal (pulse width modulation signal), or convert the output signal of a power amplifier into a PWM signal.
It may also be a WM signal. Further, a brushless DC motor may be used as the motor. Furthermore, the compensator may be constructed entirely in hardware and may perform the same operations as the program described above. In addition, various modifications can be made without changing the gist of the present invention. Effects of the Invention The motor speed control device of the present invention has extremely good control characteristics at a specific frequency, and is almost the same as the conventional control characteristics at other frequencies, and overall when the load 1 to Fluctuations in rotational speed due to fluctuations in torque are significantly reduced. Therefore, if the capstan motor of a video tape recorder is configured according to the present invention, the running speed of the magnetic tape can be controlled extremely accurately, and a high performance video tape recorder with less wow and flutter can be obtained.

[Brief explanation of drawings]

FIG. 1 is a flow diagram showing an example of the built-in program of the compensator shown in FIG. 2, FIG. 2 is a block diagram showing the overall configuration of the embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing a control block of an embodiment of the present invention, and FIG. 5 is a block diagram showing a specific example of the structure.
) 1, FIG. 6 is a flowchart showing another example of the built-in program of the compensator of the present invention, and FIG. 7 shows another example of the built-in program of the compensator of the present invention. Flow diagram representing,
FIG. 8 is a diagram showing the configuration of the conventional example, FIG. 9 is a block diagram showing the control block of the conventional example, and FIG. 10 is a characteristic diagram showing the control characteristic IG(jω)1 of the conventional example. 1... Motor, 2... Rotation sensor, 3
... Speed detector, 4... Compensator, 5.
...Arithmetic unit, 6...Memory, 7...
...D/A converter, 8...Power amplifier, 10.
·····load.

Claims (1)

[Scope of Claims] 1) A rotation sensor that generates an alternating current signal with a period corresponding to the rotational speed of the motor, and a digital signal corresponding to the period of the alternating current signal of the rotation sensor Zq times (
Here, Zq is an integer of 4 or more); a compensating means that calculates and stores the digital signal of the speed detecting means to generate a control signal; power amplification means for supplying electric power to the motor; the compensation means includes rotation error detection means for detecting a rotation error E of the motor based on a digital signal from the speed detection means; A counting operation is performed in response to obtaining the signal, and Nx
・A counting means for creating a count value I whose modulus is L (where Nx is a positive number of 1 or more, and L is an integer of 4 or more), and at least N in a sequentially rewritable RAM area.
A memory means for storing xL digital values M[0] to M[NxL-1]; Digital value M [J-nL (mo
dNxL)] (n = 1, ..., Nx), and the rotation error between the calculated value obtained by the calculated value calculation means and the rotation error detection means is 1:1. The digital value of the memory means corresponding to the count value I of the counting means is sequentially changed to M[0], M[0],
an update storage means for updating and saving M[1], M[2], ... in the order;
a control signal generating means for generating the control signal by adding and combining the calculated value obtained by the calculated value calculating means and the current rotational error of the rotational error detecting means at a ratio of D:1; A speed control device for a motor, characterized in that the ratio D is 0.25≦D≦0.5. (2)
Claim No. (1) characterized in that Nx≧2.
) Speed control device for the motor described in item 2. (3) The calculated value calculation means calculates a group of digital values M [J-nL (mod NxL)] (n=1, 2, . . . separated by L intervals in the RAM area of the memory means).
. . . , Nx) are each given a predetermined positive ratio Wn (n=
1, 2, ... ..., Nx) (here, 0<Wn<
2/Nx and ▲There are mathematical formulas, chemical formulas, tables, etc.▼, and then additive synthesis is performed to obtain a calculated value that substantially corresponds to the added value. The motor speed control device according to item (2). (4) Wn=1/Nx (n=1, 2,......N
x) A motor speed control device according to claim (3). (5) Claim (1) characterized in that L is set to a value corresponding to an integral multiple of 2 or more of one rotation period of the motor.
The speed control device for the motor described in Section 1. (6) The update storage means obtains an added value by adding the calculated value obtained by the calculated value calculation means and the rotation error of the rotation error detection means at a ratio of 1:1, and adds the calculated value obtained by the calculated value calculation means and the rotation error of the rotation error detection means at a ratio of 1:1, and Claims characterized in that a value obtained by adding and combining the values multiplied by a predetermined positive ratio is set as a new update value, and is stored as a digital value in the memory means corresponding to the count value of the counting means. The motor speed control device according to item (1). (7) The first calculated value of the calculated value calculating means used in the control signal generating means is substantially Nx digital values M[J1-nL (mod NxL)] (n=1, . . . ..., Nx)
The second calculated value of the calculated value calculation means used in the update storage means is calculated using the other Nx digital values M[J2-nL(mo
d NxL)] (n = 1, ..., Nx), and the integers J1 and J2 change according to the count value I of the counting means, and J1 = J2 + Px (mod Nx
The motor speed control device according to claim 1, characterized in that there is a relationship as follows: L) (where Px is an integer of 1 or more and 5 or less). (8) The calculated value calculating means is a count value I of the counting means.
Nx digital values M[J-nL (mod NxL)] (n=1,...,Nx) in the memory means
A patent claim characterized in that an added value is obtained by adding and combining the above, and further, a value obtained by multiplying a plurality of consecutive added values with respect to the integer J by a predetermined positive ratio is added and combined to obtain a calculated value. A speed control device for a motor according to scope (1).