JPS60229143A - Program transfer method of computer - Google Patents

Abstract

PURPOSE:To attain an error detection function of a processing procedure in addition to the error detection in word unit by having the identification code of a program word to be executed next during the program processing. CONSTITUTION:A designated address of a memory part 9 is outputted to an address bus 4 via an address buffer 3 under the program processing control of an arithmetic control part 2. At the same time, an identification code of a program word of said address is outputted to an identification code generating circuit 19. When an address is set, an OP designated word 16b, a parity bit 17b and a word identification code 21b, for example, of a designated address are outputted from the part 9. Then a memory read signal is outputted through a control bus 6 and then loaded to a parity check circuit 13, a data register 7 and an identification code comparator 20 respectively via a data buffer 12. Then the code 21b is compared with an identification code outputted from the circuit 19. An error signal is outputted when no coincidence is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a program transfer method for detecting a failure in a storage unit of a computer system. In recent years, with the development of high-density LSI technology, the storage section (
ROM, RAM, etc.) and CPU units (microprocessors) are becoming smaller and their packaging density is also increasing.

Riding on this wave of LSI development, for example, computers are being used in the field of artificial satellites for the purpose of multifunctionality and higher precision.

However, in the case of long-term operation in outer space where maintenance is not possible, such as with the 9-satellite, high reliability is required, and by simplifying the circuit design and reducing the number of parts, it is necessary to create a compact, lightweight, and low-cost structure. Reducing power consumption has become an important issue.

Most computer failures occur in the highly integrated parts of the storage section and CPU section, but they often occur particularly in the storage section, which has a large number of components, and is a major factor in reducing reliability.

Particularly in the case of artificial satellites, the biggest problem is storage failure due to the effects of radiation in the space environment.

Of all the failures in this storage unit, the most serious effect is a program failure, and if left untreated, the program will run out of control, which will have a great impact on the attitude system of the satellite (for example), and the final It is fully expected that this will lead to overall failure, such as shortening the lifespan of the satellite.

Therefore, the biggest challenge in failure detection is to minimize the effects of failures by detecting and treating them as quickly as possible.

This invention describes the flow of program processing in the storage unit.

It is monitored by adding a word identification code, and if the type of word to be transferred is different from the one specified by the CPU section, a malfunction is detected before the first program word is read to prevent runaway etc. The purpose is to prevent erroneous processing.

[Prior Art] Although there is no example of checking the operation flow of a program in the conventional program transfer method, this is a method of checking the stage reversal error of each word constituting the program in the storage unit on a word-by-word basis.

There were parity check methods and error correction code methods. The former only detects logical inversion errors in words, but the latter has an error correction function in addition to error detection.

However, in any case, these methods are checking methods for each word, and do not have a function of checking the operation flow.

FIGS. 1 and 2 show a parity check method as a conventional example. In FIG. 1, (1) is the CPU section.

(2) is an arithmetic control unit that controls the decoding and execution of programs.

(3) is an address buffer that specifies the storage address of the program; 141 is an address bus; (5) is an III buffer that controls program read/write or various processing; and (6) is a control bus.

(7) is a data register that latches a program word, and (8) is a bidirectional data bus. (9) is a storage section, IIG is a program area composed of a plurality of program words, and Qll is a parity pit area attached to each program word. α side is memory 5 (
9) A bidirectional data bus buffer that transfers the parity pits and program words output from the data bus buffer t13, (13 is a parity check circuit that checks program word errors based on the output information of the data bus buffer t13, Error judgment circuit.

a9 is an error identification signal.

FIG. 2 shows an example in which the inside of the storage section (9) is subdivided.

An example is shown in which 1 bit is assigned as the parity pit area a0, and (17a) to (17g) indicate parity pits assigned to each word. Program area staff.

It consists of multiple program words.

(16a) to (ISd) are operation designation words (OP designation words) that indicate the processing mode of the program.

(16θ) is a data specification word that is paired with an OP specification word (16b) and indicates immediate data, and (16f) is an O
A direct addressing word + (16
g) is an indirect addressing word that is paired with the op designation word (16d) and indicates an address where data is stored (or where data is to be loaded).

OP designation word (16b) and data designation word (16b)
Paired program words such as θ) must be executed as a pair before the OP designation word (161)) is executed before the data designation word (16θ) is processed.

Next, the operation will be explained.

By the program processing control of the arithmetic control unit (21), the storage unit (9) is transferred to the address bus (4) via the address buffer (3).
) is output.

With this address designation, 1, for example, OP designation word (1
6b) and the harness pit (17b) are output to the data bus buffer α. Then the control signal buffer 15)
A program read signal is output to the control bus (6), and after opening the gate around the data bus buffer a, it is output to the data bus (8), and the OP specified word (i6b) and parity pit (17b) are Loaded into data register (7) and parity check circuit 0.

The parity check circuit αJ performs a parity check on this one word and outputs the result to the error determination circuit α4. When an error occurs, the error identification signal U! Outputs the error status to 9. When there is no error, the operation control unit (2) decodes the OP designation code (16b) loaded into the data register (7) and reads the 9th data designation word (16e) and parity pit (17e) in the same way. The data is loaded into the data register (7) and the parity check circuit +13 using the following procedure, and a parity check is performed on this one word.

In this way, the parity check method is a method of checking for logic inversion errors word by word when program words are sequentially stored from the storage section (9) and loaded into the CPU section.

For this reason, for example, a temporary error in the CPU section (1) may occur.

An error occurred when decoding the OP designation code (16t+), and the data designation word (16θ) that was supposed to be loaded next could not be loaded.For example, even if the OP designation word (16c) was loaded, an error could not be determined and the OF Specified word (
16c) as the data specification word (16e) and the program's operation sequence will be combined. Also, especially in jump instructions, etc.

It had the drawback that it was unable to detect errors even when the address to jump to was accidentally loaded.

[Summary of the Invention] This invention was made to improve these drawbacks in the process of program processing.

By providing an identification code of the program word to be processed next, a method is provided that can provide an error detection function of the program processing procedure in addition to the error detection of each word of the program word.

[Embodiments of the invention] FIG. 3 shows an embodiment of the present invention.

+II is a word identification code area that indicates the type of each constituent word in program area 4, such as whether the word is an OP designation code (16a) to (16cL) or a data designation word (16e), and al is a storage unit. (9) An identification code generation circuit that generates the type of program word to be loaded next into the data register xl 171; Information and identification code generation circuit fi
This is an identification code comparison circuit that compares both pieces of code information generated from I.

FIG. 4 is a detailed diagram of the storage section (9) in FIG. 3.

The word identification code area (l[6 is an example in which a program word is identified with 4 bits, and a 2-bit humming key on the upper side is adopted. (21a) to (21g) are the codes attached to each program word. This is a word identification code.

In the assignment of word identification codes (21a) to (21g), (no label) means that it is not a jump destination from another program word, and (with label) means that it is not a jump destination from another program word. Indicates that it is specified as the jump destination from word.

In this way, the word identification codes (21a) to (21g) are designed so that they do not shift to other codes even when one bit of logic is inverted.

Next, the operation will be explained.

The basic program transfer procedure between the CPU section (1) and the memory 5 (9) is the same as that of the conventional example shown in FIG. 1, but the following processing is added.

That is, when the specified address of the storage section (9) is outputted to the address bus (4) via the address buffer (3) under the program processing control of the arithmetic control section (2), the identification code of the program word of the specified address is simultaneously output as an identification code. Output to the generation circuit (II).

When the address is set, for example, the OF designation word (161)), parity bit (171)) and word identification code (21b) of the specified address are stored in the storage unit (9).
is output, and then a memory read signal is output from the control bus (6) and is loaded into the parity check circuit UL*data register (7) and the identification code comparison circuit via the data bus buffer U3. The identification code comparison circuit (2) compares the word identification code (21b) output from the data bus buffer α with the identification code output from the identification code generation circuit ul.

- When it is pasting, it outputs a coincidence signal to the error judgment circuit tut, and when it does not match, it outputs an error signal. For example, when a jump instruction occurs and the program flow changes, the identification code generation circuit ■ generates an identification code (with a label).
It is supposed to be set in the OP designation word (1001) of 16(1), but 9 For example, if an identification code other than this is output from the storage unit (9).

This can be identified as an error in the jump destination of the program.

For example, when the OP designation word (16c) is executed, the word identification code (21f) directly indicates the address designation word (16f) to the identification code generation circuit tpi as the next identification code to be loaded from the storage unit (9). ) of (ol
ot) should be output. However, the word identification codes (21a) to (21g) loaded from the storage unit (9)
If it is other than this, it can be identified as a program flow error.

In this way, the identification code generation circuit generates the identification code of the next program word to be loaded from the storage unit (9) in advance.
11, and by comparing the word identification codes (21a) to (21g) actually output from the storage unit (9), it can be determined whether the program flow is running normally. It has characteristics.

Although one or more of the above embodiments have been described as being applied to, for example, a computer system for an artificial satellite, the present invention is not limited to this and may be applied to any computer system that requires countermeasures against errors.

[Effects of the Invention] As described above, according to the present invention, a word identification code area is arranged in the storage section and an identification code generation circuit is arranged in the CPU section, and when loading a program from the storage section, the identification code generation circuit Next, an identification code for the program word to be loaded is generated, and an identification code comparison circuit compares it with the word identification code output from the storage unit at the time of loading, thereby determining whether or not the program word should originally be transferred. Has discernible advantages.

In other words, you can check the program processing flow,
This has the advantage of being able to prevent errors in program processing due to errors in the storage unit.

[Brief explanation of drawings]

Figure 1 shows the conventional parity check method, Figure 2 shows the conventional parity check method.
1, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 4 is a diagram showing the configuration of the storage section in FIG. 3. In the figure, (1) is the CPU section, (2) is the calculation control section, (3)
is the address buffer, (5) is the control signal buffer, (9
) is the storage section, (1e is the program area, αD is the parity bit area, (Muken is the parity check circuit, α-fold end error judgment circuit, us is the word identification code area, aI is the identification code generation circuit, (to) is This is an identification code comparison circuit. Identical or corresponding parts in Figure 1 are indicated with the same reference numerals. Agent Masuo Oiwa Proceedings Amendment (Method) May 29, 1930 1, Indication of Case Japanese Patent Application No. 512211197 3, Part 6 to Hitoshi Katayama, representative of the person making the amendment, Detailed explanation of the invention in the specification subject to the amendment 1, Page 2, lines 10 and 11 of the description of the contents of the amendment Insert “Elephant: Detailed description of the invention” between.

Claims (1)

[Scope of Claims] A program consisting of a CPU unit, a storage unit, and a plurality of combinations of operation designation words, address designation words, and data designation words arranged on the storage unit,
By specifying the program storage address of the storage section from the U section, each word constituting the program is stored in order from the storage section. In a computer program transfer method in which the program is transferred to the CPU section and decoded and executed by the CPU section, a bit key for identifying it is added to each of the operation slip word 1 address specification word and data specification word that constitute the program on the storage section. an identification code generating circuit which generates in advance an identification code of the program word to be read next from the storage section in the 0PTI section; By adding an identification code comparison circuit that compares the identification code. Each time a program word is read from the storage section according to instructions from the CPU section, the identification code comparison circuit compares the identification code set in advance in the identification code generation circuit with the word identification code added to each word of the program, and determines whether they match or do not match. A program transfer method for a computer, characterized in that it is possible to determine whether or not the transferred program is a word of a specified type in the CPU section by