JPS6379378A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the electrostatic breakdown strength of an output circuit and to prevent defective operation, by providing a doubledrain structure for an MISFET in an inner circuit, and providing a single-drain structure, which has double drains at a part, for an MISFET at an output stage. CONSTITUTION:In an MISFET Qn, a semiconductor region 7 is formed around the outer surface of a semiconductor region 8. Thus, the electric field strength in the vicinity of a drain region can be weakened with the semiconductor region 7 having low impurity concentration. The drain region of an MISFET Q1 in an output stage circuit and the source region of an MISFET Q2 are constituted with a single-drain structure, which has double drains at a part of a channel forming region. Thus the electric field strength in the vicinity of the drain region and the source region can be weakened with the semiconductor region 7 having low impurity concentration.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device.

The present invention relates to a technique that is effective when applied to the output circuit.

[Conventional technology]

A push-pull type inverter circuit is used as an output circuit (output buffer 7 circuit) of a semiconductor integrated circuit device. This inverter circuit has MI for driving and load.
Each of the S FETs is an enhancement type n-channel MISFET.

This type of semiconductor integrated circuit device is highly integrated and MIS
As the size of the FET decreases, the electric field strength near the drain region increases, causing the generation of hot carriers to become a problem. Hot carriers are generated in the gate insulating film and in the gate insulation film.
'It is trapped at the interface between the film and silicon, and the MISFET
This causes the threshold voltage of the device to change over time.

To prevent the generation of such hot carriers, MI
It is necessary to adopt a so-called double drain structure for the SFET. In a MISFET with a double drain structure, a drain region is composed of an n° type (high impurity concentration) semiconductor region and an n type (low impurity concentration) semiconductor region formed along the outer periphery of the n° type (high impurity concentration) semiconductor region.

Since the double drain structure can weaken the electric field strength near the drain region in the n-type semiconductor region, it can reduce the generation of hot carriers described above. The double drain structure is adopted for all MISFETs in the internal circuit, input circuit, and output circuit to reduce the manufacturing process.

However, according to Japanese Patent Application No. 59-240619 previously filed by the applicant, the output circuit (hereinafter also referred to as the output stage circuit) is an M I S with a double drain structure.
It is stated that when 48 FETs are used, a double point occurs between the following times, and a means for solving this problem is described.

A drive or load MIS FET with a double drain structure that constitutes an output stage circuit constitutes an electrostatic breakdown prevention circuit (diode element) with a drain region or a source region and a semiconductor substrate. This electrostatic breakdown prevention circuit is essentially composed of an n-type (low impurity concentration) semiconductor region and a semiconductor substrate, so it has a higher breakdown rate than a circuit that is composed of an n-type (high impurity concentration) semiconductor region. Voltage increases. Therefore, the output stage circuit suffers from electrostatic damage before the semiconductor substrate side absorbs the excessive voltage that induces electrostatic damage.

Therefore, in order to solve this problem, the output stage circuit is configured with a single drain structure MISFET, and the internal circuit is configured with a double drain structure MISFET.

The semiconductor integrated circuit device configured in this way can prevent the generation of hot carriers in the internal circuit, so the M
I S FET threshold (prevents fluctuations in IT voltage,
It has the feature of improving electrical reliability. In addition, the breakdown voltage of the electrostatic breakdown prevention circuit inserted in the output stage circuit is lowered, and excessive voltage can be absorbed into the semiconductor substrate before the output stage circuit causes electrostatic breakdown, improving the electrostatic breakdown voltage. There are features that allow it.

[Problem that the invention seeks to solve]

The inventors of the present invention discovered the following problems as a result of testing and examining the operating characteristics of the output stage circuit described above.

The drive and load MISFETs of the output stage circuit have a so-called single drain structure in order to improve electrostatic breakdown voltage. MISFE with single drain structure
In T, during operation, the electric field strength near the drain region is high, so the generation of hollow L-carriers is significant. Among the hot carriers, holes act as a substrate current and raise the substrate potential of the output stage circuit. For this reason, it becomes impossible to ensure a sufficient potential difference between the source or drain region and the substrate, especially when input and output are applied to a common terminal (
I10 common), a problem arises in that the margin of the standard voltage on the low level side of the input signal of that terminal (hereinafter referred to as the "I/O" terminal) is reduced. Also.

If the substrate potential rises significantly, malfunctions occur in the output stage circuit and internal circuits.

An object of the present invention is to provide a technique that can improve the electrostatic breakdown voltage of an output circuit in a semiconductor integrated circuit device and prevent malfunction thereof.

Another object of the present invention is to provide a technique that can expand the standard voltage margin on the low level side of the input signal to the I10 terminal.

Another object of the present invention is to provide a technique capable of achieving the above object and improving the electrical reliability of the internal circuit.

Another object of the present invention is to provide a technique capable of achieving the above object and increasing the operating speed of an output circuit.

The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.

[Means for resolving the shortcomings]

An overview of one typical invention disclosed in this application is as follows.

In a semiconductor integrated circuit device, MISFET in the internal circuit
1 and 3 with a double drain structure, and MI of the output stage circuit.
The SFET is configured with a single drain structure having a double drain structure in a portion on the side of the channel formation region.

[For production]

According to the above-described means, it is possible to reduce the deterioration of the threshold voltage over time caused by hot carriers in the MISFET of the internal circuit, so that the electrical reliability can be improved. Furthermore, in addition to this, a double drain t+ is formed in the output circuit to reduce the generation of hot carriers and reduce the substrate current, thereby preventing malfunctions.

The single-drain structure reduces breakdown voltage and allows excessive voltage to be absorbed immediately on the substrate side, thereby preventing electrostatic damage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with one embodiment in which the present invention is applied to a semiconductor integrated circuit device in which an output stage circuit is configured with a push-pull type inverter circuit.

In all the figures, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.

〔Example〕

An output section of a semiconductor integrated circuit device according to an embodiment of the present invention is shown in FIG. 1 (equivalent @ circuit).

As shown in FIG. 1, the output stage circuit of a semiconductor integrated circuit device is comprised of a push-pull type inverter circuit. That is, this inverter circuit has a driving M I S
It is composed of a FETQs and a load MISFET Q2, each of which is an n-channel enhancement type.

The drain region of the driving MISFET Q I and the source region of the load MISFET Q 2 are connected to each other and to an external output terminal (bonding pad) BP. MISFE for drive
TQ has a reference voltage (for example, ground potential of one circuit 0 [V]) Vss connected to its source region, and is configured to output a low-level output signal. MI for load
5FETQ2 has a power supply voltage (for example,
The operating voltage of the circuit (5 [V]) Vec is connected, and the circuit is configured to output a high level output and signal.

MI 5FETQ+ for drive, M r SF for load
Each gate electrode of ETQ2 has an output (No. 8 terminal,
D, respectively. The output signal terminal D is adapted to display an output signal from the internal circuit.

The output stage circuit configured in this way usually has a voltage of V3s to V3s.
Outputs an output signal within the range of cc-Vjh (L threshold voltage). In the I10 common output stage circuit mounted on SRAM, DRAM, etc., a VgB potential (for example, -2,5 to -3,5 [V'l) is applied to the board, and the input horn signal of the I10 terminal is The standard voltage on the low level side is -3.0[V
] Guaranteed up to a certain extent. If it is considered as I10 common,
The output terminal BP in FIG. 1 is the I10 terminal, and the CM OS (
Needless to say, a complementary MO8) inverter circuit (not shown) is connected. Note that this p channel and n
The channel MISFET Tr is approximately the same as the p-channel and n-channel MISFETs QP and Qn of the internal circuit, which will be described later.
Furthermore, the CMO as this input stage circuit is configured as follows.
In order to protect the S inverter circuit from electrostatic damage, an n-channel M connected in diode form with a resistive element, for example.
A protection circuit consisting of an IS FET is added. The MISFET of the protection circuit may be formed only in a semiconductor region 8, which will be described later; therefore, its source and drain regions may be formed.

Next, the specific configuration of the output stage circuit will be explained with reference to FIG. 2 (cross-sectional view) together with the MISFET Tr of the internal circuit.

In FIG. 2, 2 is a p-type semiconductor substrate made of single crystal silicon, and 2 is an n-type well region.

A substrate potential v81 is applied to the semiconductor substrate 1, and a power supply voltage Vcc is applied to the well region 2.

A field insulating film 3 and a p-type or n-type channel stopper region 4 are provided on the main surfaces of the semiconductor substrate 1 and the overlayer region 2 between the M I S FET formation regions.

These are configured to provide electrical isolation between the M I S l''ET.

Internal circuit n-channel M I S F E T Q n
is formed on the main surface of the semiconductor substrate 1 within a region surrounded by the field insulating film 3. In other words, MISFET Q
n is composed of a gate insulating film 5, a gate electrode 6, a pair of n-type semiconductor regions 7 and n'-type semiconductor regions 8, which are source or drain regions. The semiconductor region 7 with a low impurity concentration is made of phosphorus, and the semiconductor region 8 with a high impurity concentration is made with arsenic. That is, the source region and the drain region are formed by utilizing the difference in diffusion speed between the two, and since the diffusion speed of phosphorus is faster than that of arsenic, the semiconductor region 7 is formed along the outer periphery of the semiconductor region 8. ing. This M I S FET Q n has a so-called double drain structure.

In this way, the internal circuit n-channel MISFET Q
By configuring n with a double drain structure, the electric field strength near the drain region can be weakened by the semiconductor region 7 with a low impurity concentration, so the generation of hot carriers can be reduced. In other words, it is possible to reduce deterioration of the threshold voltage of MISFETQn over time, thereby improving electrical reliability.

The p-channel MISFET QP of the internal circuit is formed on the main surface of the well region 2 in a region surrounded by the field insulating film 3. That is, the MISFET Qp is composed of a gate insulator yA5, a gate electrode 6, and a pair of p''' type semiconductor regions 9 that are a source region or a drain region.

For driving the output stage circuit M r S F E T Q t
, and the load MISFET Q 2 are formed on the main surface of the semiconductor substrate 1 in a region surrounded by the field isolation B film 3.

Each of the 5FETs Q+ and Q2 is composed of a semiconductor substrate 1, a gate insulating film 5, a gate electrode 6, a pair of n-type semiconductor regions 7 and n-type semiconductor regions 8, which are source or drain regions. The semiconductor region 7 with a low impurity concentration is formed only in a part of the channel forming region side. In other words, MISF E TQ +, , ()
Each of the transistors 2 has a single train structure having a double drain structure in a part on the side of the channel forming region. Drain region of M I S F E T Q +, M
A highly impurity-concentrated semiconductor region 8 used as a source region of the I5FETQ2 constitutes a diode element at a pn junction with the semiconductor substrate 1. This diode element constitutes an electrostatic breakdown prevention circuit of the output stage circuit.

The semiconductor region 7 with a low impurity concentration is formed as shown in FIG. 3 (a cross-sectional view in a predetermined manufacturing process). In other words,
The semiconductor region 7 includes MI 5FETQ+ of the output stage circuit,
Mask 1 for forming each of Q2 into a single drain structure
It can be formed by partially changing the pattern of No. 3 and introducing phosphorus by ion implantation using this mask 13. The semiconductor region 7 is formed in the same process for the internal circuit and the output stage circuit, and is formed by M, I S F E T Q
+ and Q2 are formed in a self-aligned manner with respect to the respective gate electrodes 6.

The mask 13 is formed of, for example, a photoresist film.

Although not shown, there is also an n-channel MISF for clamping the electrostatic breakdown prevention circuit provided before the input stage circuit.
ET is configured with a single drain structure (semiconductor region 8).

As shown in FIG. 3, the semiconductor region 8 with high impurity concentration is
It can be formed by introducing arsenic by ion implantation using the mask 14. Similarly to the semiconductor region 7, the semiconductor region 8 is formed by the internal circuit and the output stage circuit in the same process.

In this way, at least the MISF E of the output stage circuit
Train region of T Q l, M I S F E T
By configuring the source region of Q2 with a single drain structure having a double drain structure in a part on the side of the channel formation region, it is possible to weaken the electric field strength near the drain region and the source region in the semiconductor region 7 with a low impurity concentration. Therefore, generation of hot carriers can be reduced. In other words, it is possible to reduce the substrate current and reduce the floating of the substrate potential of the semiconductor substrate 1 in the output stage circuit portion.
The margin of the standard voltage on the low level side of the input signal to the I10 terminal can be expanded. Moreover, malfunction of the output stage circuit can be prevented.

Also, as mentioned above, ~ I I S F E T Q
By configuring the drain region of 1 and the source region of MISFET Q 2 with a single drain structure, an electrostatic breakdown prevention circuit (diode element) consisting of a pn junction between the semiconductor region 8 and the semiconductor substrate 1 is formed. Since the breakdown voltage can be lowered, excessive voltage can be absorbed into the semiconductor substrate l side before the output stage circuit is damaged by static electricity.

In addition, by configuring a part of the channel formation region side of MI 5FETQ+, Q2 with a double drain structure,
Since the diffusion distance of phosphorus forming the semiconductor region 7 toward the channel forming region side is long (compared to arsenic), the channel length can be reduced.

Reducing the channel length can lower the resistance value and threshold voltage of each channel forming region (between the source region and the train region) of M I 5FETQ+ and Q2.

In other words, it is possible to increase the operating speed of the MI S FETs Q+ and Q2.

These individual effects are caused by the internal circuit MISFETQn,
The electrical reliability of Qp can be improved and obtained.

Also, reducing the substrate current is particularly effective when applied to the output stage circuit connected to the I10 terminal, while reducing the resistance value and threshold voltage increases the speed of the output stage circuit connected to the output terminal. It is particularly effective for

10 is an interlayer insulating film covering MI 5FETQn, Qp, Q+ and Q2, 11 is a connection hole, and 12 is a wiring (for example, an aluminum film).

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the present invention, a plurality of drive MIs connected in parallel
An output stage circuit may be configured with a plurality of load MISFET Qs 2 connected in parallel in the same way as SFETQl.

Further, the present invention provides a load M I that constitutes an output stage circuit.
S F E T Q 2 may be configured as a load element whose gate electrode and drain region are short-circuited.

Further, the present invention provides drive and load MISFET Q
I and Q2, L D D (Light, 1ydan o
It can be configured with a ped-rain) structure. The MISFET in the internal circuit has a double drain structure.

In an LDD structure MISFET, an n-type semiconductor region with a low impurity concentration is formed using the gate electrode as a mask, a sidewall spacer is formed on the side of the gate electrode, and then a rl" type semiconductor region with a high impurity concentration is formed using the spacer. It can be configured by forming.

〔Effect of the invention〕

As explained above, the effects that can be obtained by one representative invention among the inventions disclosed in this application will be briefly described as follows.

In the M I S FET of the internal circuit of the semiconductor integrated circuit device, it is possible to reduce the deterioration over time of the threshold direct pressure caused by hot carriers, so that the electrical reliability can be improved.

Furthermore, in the output stage circuit, the double drain structure can reduce the generation of hot carriers and reduce the substrate current, preventing the operating element rt, and the single train structure can reduce the breakdown voltage. Since excessive voltage can be immediately absorbed on the substrate side, electrostatic damage can be prevented.

[Brief explanation of the drawing]

FIG. 1 shows an equivalent circuit diagram of an output section of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 shows a specific configuration of the output section and internal circuit shown in FIG. Cross-sectional view FIG. 3 is a cross-sectional view of the output section and internal circuit shown in FIG. 2 in a predetermined manufacturing process. In the figure, 1... semiconductor substrate, 2... well region, 5 gate insulating film, 6... gate electrode, 7, 8.9... semiconductor region, Q... drive MI 5FET, Q2 ・
・Load MISFET, Qp, Qn=・L113FE-
r, BP...External output terminal, Vss...Reference voltage, V
cc...Electricity'rXf11 voltage.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device including a MISFET in each of an internal circuit and an output circuit, a MISFET in the internal circuit
The source region or the drain region of T is formed by a first semiconductor region with a high impurity concentration and a region formed along the outer periphery of the first semiconductor region, which has the same conductivity type as the first semiconductor region and has a lower impurity concentration than the first semiconductor region. a second semiconductor region, and a source region or a drain region of the MISFET of the output circuit is composed of the first semiconductor region and a part of the second semiconductor region formed on the channel forming region side. A semiconductor integrated circuit device characterized by: 2. The MISFET of the internal circuit is configured with a double drain structure, and the MISFET of the output circuit is configured with a single drain structure with a part of the double drain structure. 2. The semiconductor integrated circuit device described in 2. 3. The output circuit is comprised of a push-pull type inverter circuit consisting of drive and load MISFETs of the same channel type.
2. The semiconductor integrated circuit device described in 2.