JPS6379333A - Fine wire of high-purity refined copper for semiconductor device - Google Patents

Fine wire of high-purity refined copper for semiconductor device

Info

Publication number
JPS6379333A
JPS6379333A JP61224298A JP22429886A JPS6379333A JP S6379333 A JPS6379333 A JP S6379333A JP 61224298 A JP61224298 A JP 61224298A JP 22429886 A JP22429886 A JP 22429886A JP S6379333 A JPS6379333 A JP S6379333A
Authority
JP
Japan
Prior art keywords
wire
less
bonding
unavoidable impurities
hardness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61224298A
Other languages
Japanese (ja)
Other versions
JPH0744196B2 (en
Inventor
Naoyuki Hosoda
細田 直之
Toshiaki Ono
敏昭 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Metal Corp
Original Assignee
Mitsubishi Metal Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Metal Corp filed Critical Mitsubishi Metal Corp
Priority to JP61224298A priority Critical patent/JPH0744196B2/en
Publication of JPS6379333A publication Critical patent/JPS6379333A/en
Publication of JPH0744196B2 publication Critical patent/JPH0744196B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the damage to an Si chip surface at the time of ball bonding at high speed, by setting the contents of S and C components as unavoidable impurities at specified values respectively, and making the total content of the unavoidable impurities less than or equal to 5ppm. CONSTITUTION:The contents of S and C components as unavoidable impurities are set as follows; S is less than or equal to 0.5ppm, and C is less than or equal to 1ppm. The total content of unavoidoble impurities is made less than or rqual to 5ppm. As the result, the hardness of a ball part formed at the tip of a wire becomes relatively low, and the change of hardness of the ball part before and after the ball bonding becomes small. Thereby, on the occasion of a high speed ball bonding, the damage to an Si chip surface is reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置の製造に際して、ボンディング
ワイヤとして用いた場合に、ポールボンディング時のワ
イヤ先端部におけるボール部の硬さが相対的に低く、か
つボンディング時の変形に伴う加工硬化による硬さ上昇
が少ない高純度精製銅極細線に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] This invention provides a method for manufacturing semiconductor devices in which, when used as a bonding wire, the hardness of the ball portion at the tip of the wire during pole bonding is relatively low. The present invention also relates to a highly purified copper ultrafine wire that exhibits little increase in hardness due to work hardening due to deformation during bonding.

〔従来の技術〕[Conventional technology]

従来、一般に、半導体装置としてトランジスタやIC1
さらにLSIなどが知られているが、この中で、例えば
ICの製造法の1つとして、(a)  tず、リードフ
レーム素材として、板厚二0、1〜0.3 Uを有する
Cu合金条材を用意し、(b)  上記リードフレーム
素材より、エツチングまたはプレス打抜き加工にて製造
せんとするICの形状((適合したリードフレームを形
成し、(C)  ついで、上記リードフレームの所定個
所に、81チツプを、Agバーストなどの導電性樹脂を
用いて加熱接着するか、あるいは予め上記s1チップお
よびリードフレームの片面に形成しておいたAu、Ag
、 Ni、 Cu、 またはこれらの合金で構成された
めつき層を介してはんだ付けするか、さらにAuろう付
けするかし、 ((1)  上記81チツプと上記リードフレームとに
渡つて、ボンディングワイヤとして直径=20〜50μ
mを有する全極細線を用いてボールボンディングを施し
、 (e)  引続いて、上記の81チツプ、ボンディング
ワイヤ、および81チツプが取付けられた部分のリード
フレームを、これらを保護する目的で樹脂封止し、 if)  最終的に、上記リードフレームにおける相互
に連なる部分を切除してICを形成する、以上(aJ〜
(f)の主要工程からなる方法が知られている。
Conventionally, transistors and IC1s have generally been used as semiconductor devices.
Furthermore, LSI and the like are known, and among these, for example, as one of the manufacturing methods of IC, (a) t) Cu alloy having a plate thickness of 20.1 to 0.3 U is used as a lead frame material. Prepare a strip, (b) form a conforming lead frame into the shape of the IC to be manufactured by etching or press punching from the lead frame material, and (c) form a suitable lead frame at a predetermined location on the lead frame. Then, the 81 chip is heat-bonded using a conductive resin such as Ag Burst, or Au, Ag, which has been previously formed on one side of the s1 chip and the lead frame.
, Ni, Cu, or an alloy thereof, or by soldering with Au (1) As a bonding wire between the 81 chip and the lead frame. Diameter = 20~50μ
(e) Then, the 81 chip, the bonding wire, and the lead frame where the 81 chip is attached are sealed with resin for the purpose of protecting them. If) Finally, the interconnected parts of the lead frame are cut out to form an IC.
A method consisting of the main step (f) is known.

上記のように、半導体装置の製造には、ボンディングワ
イヤとして全極細線が用いられているが、近年、高価な
全極細線に代って安価な無酸素銅極細線が注目されるよ
うになっている。
As mentioned above, all ultra-fine wires are used as bonding wires in the manufacture of semiconductor devices, but in recent years, inexpensive oxygen-free copper ultra-fine wires have been attracting attention as an alternative to expensive all-extra-fine wires. ing.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、無酸素銅極細線を半導体装置のボンディングワ
イヤとして用いた場合、全極細線で通常採用されている
0、15〜0.3秒に1回の高速ボールボンディングを
行なうと、ボンディング時にワイヤ先端部に形成された
ボール部によって、例えばM合金配線被膜が破壊された
り、時にはSiチップ自体にマイクロクラックが生じた
りするなどの問題点が発生し、高速ポールボンディング
を行なうことができないのが現状である。
However, when oxygen-free copper ultrafine wire is used as a bonding wire for semiconductor devices, if high-speed ball bonding is performed once every 0.15 to 0.3 seconds, which is normally used for all ultrafine wires, the tip of the wire during bonding At present, high-speed pole bonding is not possible due to problems such as the ball part formed on the part, for example, destroying the M alloy wiring coating and sometimes causing microcracks in the Si chip itself. be.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

そこで、本発明者等は、上述のような観点から、無酸素
銅極細線のもつ上記のような問題点を解決すべく研究を
行なった結果、 (1)全極細線では、高速でのワイヤボンディング時に
、ワイヤ先端部に形成されるボール部の硬さに、ボンデ
ィング前とボンディング後にあまり変化が見られないの
に対して、無酸素銅極細線では、前記ボール部の硬さが
相対的に高く、かつボンディング後に著しい硬さ上昇が
見られ、このワイヤボール部における硬さ上昇は、ボン
ディング時の変形に伴う加工硬化に原因し、これによっ
て81チップ自体や、その表面に形成されている被膜が
損傷を受けるようになること。
Therefore, from the above-mentioned viewpoints, the present inventors conducted research to solve the above-mentioned problems with oxygen-free copper ultrafine wires, and found that (1) All ultrafine wires are During bonding, there is not much change in the hardness of the ball formed at the tip of the wire before and after bonding, whereas with oxygen-free copper ultrafine wire, the hardness of the ball is relatively different. This increase in hardness at the wire ball portion is due to work hardening due to deformation during bonding, and this causes damage to the 81 chip itself and the coating formed on its surface. becomes damaged.

(2)  このような無酸素銅極細線における高速での
ボールボンディング時に、ワイヤ先端部に形成されるボ
ール部の変形に伴う加工硬化は、通常、無酸素銅極細線
に含有する30〜l OOppmの不可避不純物、特に
5〜l Oppm含有のS成分、および3〜8 ppm
含有のC成分によってもたらされること。
(2) During high-speed ball bonding of such an ultra-fine oxygen-free copper wire, work hardening due to deformation of the ball portion formed at the tip of the wire usually occurs due to the amount of 30 to 00ppm contained in the ultra-fine oxygen-free copper wire. unavoidable impurities, especially S component containing 5-1 Oppm and 3-8 ppm
This is brought about by the contained C component.

(3)シたがって、無酸素銅極細線に不可避不純物とし
て含有するSおよびC成分の含有量を、それぞれ、 S:0.5ppm以下、 C: 1ppm以下、 に低減すると共に、不可避不純物の全含有量を5ppm
以下に低減した高純度精製銅極細線では、高速でのワイ
ヤボンディング時に、ワイヤ先端部に形成されるボール
部の硬さに、ボンディング前とボンディング後にあまシ
変化が見られず、この結果81チツプやその表面のへ!
合金配線被膜が損傷を受けることがないこと。
(3) Therefore, the contents of S and C components contained as inevitable impurities in the oxygen-free copper ultrafine wire are reduced to S: 0.5 ppm or less and C: 1 ppm or less, respectively, and all of the inevitable impurities are reduced. content 5ppm
With the ultra-fine high-purity refined copper wire reduced to below, during high-speed wire bonding, there was no noticeable change in the hardness of the ball formed at the tip of the wire before and after bonding, and as a result, 81 chips And to the surface!
The alloy wiring coating shall not be damaged.

(4)上記(3)項における不可避不純物の低減は、無
酸素銅より調整した再電解銅に、S成分を除去するだめ
の精製材として、 La 、 Ba、 Ca、 Sr 
、 Pr、Ll、Ce、Na、およびMgのうちの1種
または2種以上を、望ましくは3〜l OOppmの範
囲で含有させると共に、同時にCを除去するだめの精製
材として、Zr、 V、Ti、Nb、およびTaのうち
の1才重または2種以上を、望ましくは同じく3〜l 
OOppmの範囲で含有させた精製材含有高純度銅を用
い、これに通常の浮遊帯域溶融精製法を施すことによっ
て可能となり、この結果SおよびC成分が硫化物および
炭化物などを形成して分離されることから、これら不可
避不純物としての8およびC成分の含有量がそれぞれ、 S : 0.5 ppm以下、 C: 1ppm以下、 となると共に、その他の不可避不純物であるSe、Te
、 Fe、 Ni、C01Sn、、 As、 Sb、お
よびZnなども精製除去されることから、不可避不純物
の全含有量が5 ppm以下となること。
(4) The reduction of unavoidable impurities in item (3) above involves adding La, Ba, Ca, Sr to the re-electrolyzed copper prepared from oxygen-free copper as a refining agent to remove the S component.
, Pr, Ll, Ce, Na, and Mg, preferably in a range of 3 to 1 OOppm, and at the same time as a purification material to remove C, Zr, V, One year old weight or two or more of Ti, Nb, and Ta, preferably in the same amount of 3 to 1
This is made possible by using high-purity copper containing refining materials in the range of OOppm and subjecting it to the normal floating zone melting refining method. As a result, the S and C components form sulfides and carbides and are separated. Therefore, the contents of 8 and C components as these unavoidable impurities are as follows: S: 0.5 ppm or less, C: 1 ppm or less, and other unavoidable impurities Se and Te.
, Fe, Ni, C01Sn, As, Sb, and Zn are also purified and removed, so the total content of unavoidable impurities is 5 ppm or less.

以上(1)〜(4)に示される知見を得たのである。The findings shown in (1) to (4) above were obtained.

この発明は、上記知見にもとづいてなされたものであっ
て、不可避不純物としてのSおよびC成分の含有量を、
それぞれ、 S : 0.5 ppm以下、 C: l ppm以下、 とすると共に、不可避不純物の全含有量を5 ppm以
下とした純度をもち、特に半導体装置のボンディングワ
イヤとして用いるのに適した高純度精製銅極細線に特徴
を有するものである。
This invention was made based on the above knowledge, and the content of S and C components as inevitable impurities is
S: 0.5 ppm or less, C: 1 ppm or less, respectively, and the total content of unavoidable impurities is 5 ppm or less, and has a high purity particularly suitable for use as a bonding wire for semiconductor devices. It is characterized by refined copper ultra-fine wire.

なお、この発明の高純度精製銅極細線における不可避不
純物としてのSおよびC成分の上限値、並びに不可避不
純物の全含有量の上限値は、上記のように経験的に定め
たものであり、いずれの場合もこれらの上限値を越える
と、従来無酸素銅極細線に発生していた問題点の発生を
避けることができなくなるものです。
Note that the upper limit values of S and C components as unavoidable impurities in the high-purity refined copper ultrafine wire of this invention and the upper limit value of the total content of unavoidable impurities are determined empirically as described above. In the case of , if these upper limits are exceeded, the problems that previously occurred with ultrafine oxygen-free copper wires cannot be avoided.

〔実施例〕〔Example〕

つぎに、この発明の高純度精製銅極細線を実施例によシ
具体的に説明する。
Next, the high-purity refined copper ultrafine wire of the present invention will be specifically explained using examples.

まず、不可避不純物としてのSおよびC成分の含有量が
、それぞれS: 6ppm、 C:5ppmにして、不
可避不純物の全含有量が31 ppmの無酸素銅を用意
し、この無酸素銅に再電解を施して、S: l ppm
 、 C: 4 pI)m、および不可避不純物全含有
量: 12 ppmとした再電解銅を調製し、ついで、
この再電解銅を、真空溶解炉で溶解し、これにそれぞれ
第1表に示される割合で精製材を含有させた精製材含有
高純度銅を溶製し、直径=20、口×長さ:250朋の
寸法をもったインゴットに鋳造し、このインゴットに対
して、それぞれ真空中で4回の浮遊帯域溶融精製を施し
て、同じく第1表に示される純度をもった高純度精製鋼
とし、引続いて、この高純度精製鋼インゴットに両端部
の切除と面側を行なって、直径:15uX長さ1100
間の寸法とした状態で、通常の条件で熱間および冷間圧
延、さらに線引加工を行なって、いずれも直径:25μ
mを有する本発明高純度精製銅極細線1−28をそれぞ
れ製造した。
First, the contents of S and C components as unavoidable impurities are set to S: 6 ppm and C: 5 ppm, respectively, and oxygen-free copper with a total unavoidable impurity content of 31 ppm is prepared, and this oxygen-free copper is re-electrolyzed. S: l ppm
, C: 4 pI)m, and total unavoidable impurity content: 12 ppm, and then,
This re-electrolyzed copper was melted in a vacuum melting furnace, and high-purity copper containing refining materials was melted by adding refining materials in the proportions shown in Table 1. Diameter = 20, mouth x length: Cast into ingots having a size of 250mm, each ingot is subjected to floating zone melting and refining four times in a vacuum to produce high-purity refined steel with a purity also shown in Table 1, Subsequently, both ends of this high-purity refined steel ingot were cut and the face side was cut to a diameter of 15u x length of 1100mm.
With the dimensions between
High-purity refined copper ultrafine wires 1-28 of the present invention having a diameter of m were manufactured, respectively.

また、比較の目的で、上記の無酸素銅および再電解銅か
ら同一の条件で、それぞれ無酸素銅極細線および再電解
銅極細線を製造した。
Further, for the purpose of comparison, an oxygen-free copper extra-fine wire and a re-electrolyzed copper extra-fine wire were produced from the above-mentioned oxygen-free copper and re-electrolyzed copper under the same conditions, respectively.

ついで、この結果得られた各種の極細線をボンディング
ワイヤとして用い、M合金配線被膜を有するS1チツプ
に0.15秒/回の高速でポールボンディングを行ない
、ワイヤ先端部に形成されたボール部のボンディング前
とボンディング後の断面硬さをビッカース硬さにて測定
すると共に、1万回のボンディングで前記被膜に発生し
た損傷回数を測定した。
Next, using the various ultrafine wires obtained as bonding wires, pole bonding was performed at a high speed of 0.15 seconds/time to an S1 chip having an M alloy wiring film, so that the ball portion formed at the tip of the wire The cross-sectional hardness before and after bonding was measured using Vickers hardness, and the number of times the film was damaged during 10,000 bonding cycles was also measured.

なお、上記ボール部の断面硬さは、ボール部を無歪切断
してエツチングした状態のものを超微小マイクロビッカ
ース硬度計((て測定した。
The cross-sectional hardness of the ball portion was measured using an ultra-fine micro Vickers hardness meter (()) after cutting and etching the ball portion without strain.

〔発明の効果〕〔Effect of the invention〕

第1表に示される結果から、本発明高純度精製銅極細線
1〜28においては、不可避不純物としてのSおよびC
成分の含有量が、それぞれS:O5ppm以下、C二1
ppm以下と低く、かつ不可避不純物の全含有量も5 
ppm以下と低いので、ワイヤ先端部に形成されるボー
ル部の硬さが相対的に低く、かつポールボンディング前
後におけるボール部の硬さ変化も少なく、この結果高速
でのポールボンディングに際して、81チツプの表面部
を傷つけることがほとんどないのに対して、無酸素銅極
細線や再電解銅極細線では、不可避不純物、特にSおよ
びC成分の含有量が高いために、ボール部のボンディン
グ後の加工硬化がはげしく、S1チツプ表面の損傷が著
しいことが明らかである。
From the results shown in Table 1, in the high-purity refined copper ultrafine wires 1 to 28 of the present invention, S and C are unavoidable impurities.
The content of the components is S:O5ppm or less, C21, respectively.
Low at less than ppm, and the total content of unavoidable impurities is 5.
ppm or less, the hardness of the ball formed at the tip of the wire is relatively low, and there is little change in the hardness of the ball before and after pole bonding.As a result, during high-speed pole bonding, the hardness of the 81 chip While the surface part is hardly damaged, oxygen-free copper ultrafine wire and re-electrolyzed copper ultrafine wire have a high content of unavoidable impurities, especially S and C components, which causes work hardening of the ball part after bonding. It is clear that the surface of the S1 chip is severely damaged.

上述のように、この発明の高純度精製銅極細線は、これ
を半導体装置のボンディングワイヤとして用いた場合、
高速でのポールボンディングに際して81チツプの表面
を損傷することがほとんどなく、金種細線に代るボンデ
ィングワイヤとして工業上有用な特性をもつのである。
As mentioned above, when the high-purity refined copper ultrafine wire of the present invention is used as a bonding wire for a semiconductor device,
There is almost no damage to the surface of the 81 chip during high-speed pole bonding, making it industrially useful as a bonding wire that can replace fine wire.

Claims (1)

【特許請求の範囲】 不可避不純物としてのSおよびC成分の含有量を、それ
ぞれ、 S:0.5ppm以下、 C:1ppm以下、 とすると共に、不可避不純物の全含有量を5ppm以下
とした純度をもつことを特徴とする半導体装置用高純度
精製銅極細線。
[Claims] The content of S and C components as unavoidable impurities is respectively S: 0.5 ppm or less and C: 1 ppm or less, and the purity is such that the total content of unavoidable impurities is 5 ppm or less. High-purity refined copper ultrafine wire for semiconductor devices, which is characterized by having
JP61224298A 1986-09-22 1986-09-22 High-purity refined copper ultrafine wire for semiconductor devices Expired - Lifetime JPH0744196B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61224298A JPH0744196B2 (en) 1986-09-22 1986-09-22 High-purity refined copper ultrafine wire for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61224298A JPH0744196B2 (en) 1986-09-22 1986-09-22 High-purity refined copper ultrafine wire for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS6379333A true JPS6379333A (en) 1988-04-09
JPH0744196B2 JPH0744196B2 (en) 1995-05-15

Family

ID=16811581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61224298A Expired - Lifetime JPH0744196B2 (en) 1986-09-22 1986-09-22 High-purity refined copper ultrafine wire for semiconductor devices

Country Status (1)

Country Link
JP (1) JPH0744196B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009007049A (en) * 2007-06-29 2009-01-15 Daifuku Co Ltd Freely foldable pallet for loading and unloading

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009007049A (en) * 2007-06-29 2009-01-15 Daifuku Co Ltd Freely foldable pallet for loading and unloading

Also Published As

Publication number Publication date
JPH0744196B2 (en) 1995-05-15

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