JPH0237698B2 - - Google Patents

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Publication number
JPH0237698B2
JPH0237698B2 JP58075334A JP7533483A JPH0237698B2 JP H0237698 B2 JPH0237698 B2 JP H0237698B2 JP 58075334 A JP58075334 A JP 58075334A JP 7533483 A JP7533483 A JP 7533483A JP H0237698 B2 JPH0237698 B2 JP H0237698B2
Authority
JP
Japan
Prior art keywords
wire
diameter
less
hardness
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58075334A
Other languages
Japanese (ja)
Other versions
JPS59201454A (en
Inventor
Naoyuki Hosoda
Masayuki Tanaka
Tamotsu Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Metal Corp
Original Assignee
Mitsubishi Metal Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Metal Corp filed Critical Mitsubishi Metal Corp
Priority to JP58075334A priority Critical patent/JPS59201454A/en
Publication of JPS59201454A publication Critical patent/JPS59201454A/en
Publication of JPH0237698B2 publication Critical patent/JPH0237698B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45164—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/012—Semiconductor purity grades
    • H01L2924/01204—4N purity grades, i.e. 99.99%

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To increase the loop height after bonding and eliminate the Al exclusion phenomenon at an Al-pad by a method wherein, when a Pd fine wire for bonding is produced, Pd of the purity of not less than 99.995 weight % is used and contents of Pt and Fe, which are unavoidable impurities, are not more than 15ppm each and the hardness of a ball formed to the tip of the wire is less than 60 in Vickers hardness. CONSTITUTION:Melted Pd, whose purity is not less than 99.995 weight % and whose contents of Pt and Fe, which are unavoidable impurities, are 15ppm each, is casted into a bullet of 25mm. diameter and 150mm. length and scraped into a wire of 20mm. diameter and 140mm. length. Then the wire is subjected to the cold rolling and the vacuum intermediate annealing at 500 deg.C with the sectional area reduction rate of 35% and the diameter is reduced to 6mm.. The similar procedure is repeated and finally the wire diameter is reduced to 25mum. With this constitution, the wire is given the suitable high temperature strength and the hardness of a ball formed to the tip of the wire is suppressed less than 60 in Vickers hardness.

Description

【発明の詳細な説明】[Detailed description of the invention]

この発明は、半導体装置の製造に際して施され
るワイヤ・ボンデイングに使用するのに適した
Pd合金細線に関するものである。 一般に、半導体装置としては、トランジスタや
IC、さらにLSIなどが知られているが、例えばIC
などの半導体装置は、 (a) Cu合金の板材または条件の片面に、Au、
Ag、Ni、およびその合金などのメツキ層を形
成したものからなるリード素材を用意し、 (b) 上記リード素材にプレス打抜き加工を施して
製造せんとする半導体装置の形状に適合したリ
ードフレームとし、 (c) 上記リードフレームの所定個所に高純度Siま
たはGeなどの半導体素子を上記メツキ層を介
して熱圧着し、 (d) 上記リードフレームと上記半導体素子に対し
て、AuまたはAu合金細線を用い、熱圧着また
は超音波熱圧着法にてワイヤ・ボンデイングを
施し、 (e) 上記半導体素子、上記AuまたはAu合金細
線、および半導体素子が取付けられている部分
のリードフレームをプラスチツクでパツクし、 (f) 最終的に、上記リードフレームにおける相互
に連なる部分を切除してリード材とする、 以上(a)〜(f)の主要工程によつて製造されてい
る。 上記のように半導体装置の製造に際しては、ワ
イヤ・ボンデイング（結線）用としてAuまたは
Au合金細線を使用しているが、AuおよびAu合
金細線は、AuおよびAu合金自体が高価であるた
めに、半導体装置のコスト高の１つの原因となつ
ており、さらに結線時の高温での機械的強度、特
に破断強さが十分でないことから、高速のワイ
ヤ・ボンデイング装置を用いた場合には断線した
り、結線にたるみが生じ、シヨート（短絡）の原
因となるなどの問題点を有するものであつた。 そこで、このような問題点を解決するために、
比較的安価で、かつ高温強度を有するPd細線を、
AuおよびAu合金細線に代つて使用する試みが提
案されている。 しかし、これらのPd細線においては、ワイヤ
の先端に電弧法により形成されたボールを、熱圧
着法あるいは超音波熱圧着法により半導体素子の
アルミパツド部およびリードフレームのメツキ層
に接合するワイヤ・ボンデイングに際して、前記
ボールがビツカース硬さで60以上の高硬度をもつ
ようになることから、半導体素子上のアルミパツ
ド部にアルミ排斥現象（アルミ層が圧着される際
に外側へはみ出してしまい接合がうまくいかない
現象）が生じ、時には下地の半導体素子を破覆す
るに到るという問題点が生じ、さらに前記ボール
自体の変形も困難となるので圧着接合が不十分と
なるほか、ワイヤ自体の高温強度が高すぎること
に原因して形成されるループ高さが低く、シヨー
トの原因となるなどの問題点があるものであつ
た。 しかして、本発明者等は、上記のような従来半
導体装置のワイヤ・ボンデイング用Pd細線のも
つ問題点を解決すべく研究を行なつた結果、Pd
細線の純度を99.995重量％以上とすると共に、不
可避不純物として含有するPtおよびFeの含有量
を、それぞれ15ppm未満にすると、この結果の
Pd細線においては、ワイヤ先端に形成されるボ
ールがビツカース硬さで60未満の低硬度をもつよ
うになると共に、高温強度も上記の従来Pd細線
線に比して低いが、AuおよびAu合金に比しては
高い値をもつようになるという知見を得たのであ
る。 この発明は、上記知見にもとづいてなされたも
のであり、したがつて、Pd細線の純度が99.995重
量％未満でも、また不可避不純物としてのPtお
よびFeの含有量がそれぞれ15ppm以上になつて
も、ワイヤ・ボンデイングに際して、ワイヤの先
端部に形成されるボールの硬さをビツカース硬さ
で60未満の低硬度にすることができないばかりで
なく、ワイヤ自体の高温強度も高くなり過ぎて所
望の高いループ高さを確保することができなくな
るのであつて、かかる理由から、純度を99.995重
量％以上、不可避不純物としてPtおよびFeの含
有量をそれぞれ15ppm未満と定めたものである。 つぎに、この発明のPd細線を実施例により具
体的に説明する。 実施例 出発原料として、通常の湿式精製法および真空
溶解法により調製された、純度：99.983重量％を
有し、かつ不可避不純物としてのPtおよびFeの
含有量がそれぞれPt：26ppm、Fe：32ppmであ
り、さらに直径：25mm〓×長さ：150mmの寸法をも
つたPdビレツトを用い、このPdビレツトに所要
回数のゾーン・リフアイニング（ゾーン精製）を
繰り返し施して、第１表に示される純度、並びに
PtおよびFe含有量の精製Pdビレツトとし、つい
でこのビレツトに面削を施して直径：20mmφ×長
さ：140mmとした状態で、溝型ロールを使用し、
断面加工率：35％の条件での冷間圧延と、真空
中、温度：500℃に30分間保持の中間焼鈍とを１
サイクルとする冷間加工を繰り返し行なつて直
径：６mmφの線材とし、引続いてこの線材にダイ
ス使用による皮むき加工を施して直径：５mmφと
した後、同じくダイスを用い、断面加工率：50％
の条件での線引き加工と、真空中、温度：500℃
に20分間保持の中間焼鈍とを１サイクルとする冷
間加工を繰り返し施すことによつて、直径2.5μｍ
φの本発明Pd細線１〜７を製造した。 また、比較の目的でゾーン・リフアイニングを
省略する以外は同一の条件で未精製Pd細線を精
造した。 ついで、この結果から得られた本発明Pd細線
１〜７および未製造Pd細線について、温度：250
℃での高温破断強度と伸びを測定すると共に、先 This invention is suitable for use in wire bonding performed during the manufacture of semiconductor devices.
This relates to Pd alloy thin wire. In general, semiconductor devices include transistors and
IC and even LSI are well known, but for example, IC
Semiconductor devices such as (a) Cu alloy plate or condition have Au on one side,
Prepare a lead material made of a plating layer of Ag, Ni, or their alloys, and (b) perform a press punching process on the lead material to form a lead frame that matches the shape of the semiconductor device to be manufactured. (c) A semiconductor element made of high-purity Si or Ge is thermocompression bonded to a predetermined location of the lead frame through the plating layer, and (d) Au or Au alloy fine wire is attached to the lead frame and the semiconductor element. (e) Pack the semiconductor element, the Au or Au alloy fine wire, and the lead frame where the semiconductor element is attached with plastic. , (f) Finally, the interconnected portions of the lead frame are cut out to form a lead material. The lead frame is manufactured by the main steps (a) to (f) above. As mentioned above, when manufacturing semiconductor devices, gold or gold is used for wire bonding.
Au alloy thin wire is used, but Au and Au alloy thin wire are one of the causes of high cost of semiconductor devices because Au and Au alloy themselves are expensive. Because the mechanical strength, especially the breaking strength, is insufficient, there are problems such as wire breakage or slack in the connection when using high-speed wire bonding equipment, which may cause short circuits. It was hot. Therefore, in order to solve such problems,
Pd thin wire, which is relatively inexpensive and has high temperature strength,
Attempts have been made to replace Au and Au alloy thin wires. However, in wire bonding, these thin Pd wires bond a ball formed at the tip of the wire by electric arc method to the aluminum pad of the semiconductor element and the plating layer of the lead frame by thermocompression bonding or ultrasonic thermocompression bonding. Since the ball has a high hardness of 60 or more on the Vickers hardness scale, the aluminum pad on the semiconductor element experiences an aluminum repulsion phenomenon (a phenomenon in which the aluminum layer protrudes outward when being crimped and the bonding does not go well). This causes problems such as sometimes even destroying the underlying semiconductor element.Furthermore, it becomes difficult to deform the ball itself, resulting in insufficient pressure bonding, and the high temperature strength of the wire itself is too high. This caused problems such as the loop height formed was low and caused shoots. As a result of research to solve the above-mentioned problems with conventional Pd thin wires for wire bonding of semiconductor devices, the present inventors found that Pd
If the purity of the fine wire is 99.995% by weight or more and the content of Pt and Fe, which are unavoidable impurities, is each less than 15 ppm, this result can be improved.
In Pd thin wire, the ball formed at the wire tip has a low hardness of less than 60 on the Vickers hardness scale, and the high temperature strength is also lower than that of the conventional Pd thin wire mentioned above. They found that it has a higher value when compared to the This invention was made based on the above knowledge, and therefore, even if the purity of the Pd thin wire is less than 99.995% by weight, and even if the content of Pt and Fe as inevitable impurities is 15 ppm or more, During wire bonding, not only is it impossible to reduce the hardness of the ball formed at the tip of the wire to a low hardness of less than 60 on the Vickers scale, but the high temperature strength of the wire itself becomes too high, making it difficult to obtain the desired high loop. For this reason, the purity is set at 99.995% by weight or more, and the content of Pt and Fe as unavoidable impurities is set at less than 15 ppm each. Next, the Pd thin wire of the present invention will be specifically explained using examples. Example As a starting material, it was prepared by a normal wet refining method and a vacuum melting method, and had a purity of 99.983% by weight, and the contents of Pt and Fe as inevitable impurities were Pt: 26 ppm and Fe: 32 ppm, respectively. Furthermore, using a Pd billet with the dimensions of diameter: 25 mm × length: 150 mm, this Pd billet is repeatedly subjected to zone refining (zone refining) the required number of times to obtain the purity and purity shown in Table 1.
A purified Pd billet containing Pt and Fe was prepared, and then this billet was subjected to face cutting to a diameter of 20 mmφ x length of 140 mm, using a grooved roll,
Cold rolling at a cross-sectional processing rate of 35% and intermediate annealing at a temperature of 500°C for 30 minutes in vacuum.
A wire rod with a diameter of 6 mmφ was obtained by repeatedly performing cold working as a cycle, and then this wire rod was subjected to peeling using a die to a diameter of 5 mmφ. %
Wire drawing process under the conditions of , in vacuum, temperature: 500℃
By repeatedly performing cold working with one cycle of intermediate annealing and holding for 20 minutes, the
Pd thin wires 1 to 7 of the present invention having a diameter of φ were manufactured. In addition, for comparison purposes, unrefined Pd thin wires were refined under the same conditions except that zone refining was omitted. Next, the Pd thin wires 1 to 7 of the present invention and the unmanufactured Pd thin wires obtained from these results were heated at a temperature of 250.
In addition to measuring high-temperature breaking strength and elongation at

【表】 端部に電弧法によりボールを形成し、このボール
のビツカース硬さを測定した。 また、この本発明Pd細線１〜７および末精製
Pd細線を用いて、ワイヤ・ボンデイングを行な
い、試験片：1000個について、アルミパツド部の
排斥現象および半導体素子（Si）に破損現象が生
じた個数を測定すると共に、平均ループ高さと接
合強度（プルテスト）を測定した。これらの測定
結果を第１表に合せて示した。なお、第１表に
は、比較の目的で、直径25mmφを有するAu細線
の同一条件での試験結果も示した。 第１表に示される結果から明らかなように、本
発明Pd細線１〜７は、ワイヤ先端部に形成され
るボールの硬さが、いずれもAu細線とほぼ同じ
ビツカース硬さで60未満の低い硬さを示すことか
ら、ワイヤ・ボンデイングに際しては、アルミパ
ツド部に排斥現象も、半導体素子に破損現象も現
われず、しかも強固な接合強度を示すと共に、ル
ープ高さもAuと同様に高い値を示すものであつ
た。これに対して、純度、並びに不可避不純物と
してのPtおよびFeの含有量がこの発明の範囲か
ら外れた未精製Pd細線においては、いずれもそ
のボール硬さがビツカース硬さで60以上になつて
いるため、ワイヤ・ボンデイングに際しては数多
くのものにアルミパツド部排斥現象や半導体素子
破損現象が発生しており、しかも高温強度が高過
ぎるためにループ高さも低いものであつた。 上述のように、この発明のPd細線は、適度の
高温強度をもつために、ワイヤ・ボンデイング後
のループ高さが高く、またワイヤ・ボンデイング
に際して、ワイヤ先端部に形成されるボールの硬
さもビツカース硬さで60未満と低いために、、半
導体素子のアルミパツド部にアルミ排斥現象や半
導体素子自体に破損現象が発生することがなく、
しかも接合強度が高い状態でのワイヤ・ボンデイ
ングが可能となるなどの工業上有用な特性を有す
るのである。[Table] A ball was formed at the end using an electric arc method, and the Vickers hardness of this ball was measured. In addition, this present invention Pd thin wires 1 to 7 and powder purified
Wire bonding was performed using Pd thin wire, and the number of specimens in which the aluminum pad part was rejected and the semiconductor element (Si) was damaged was measured for 1000 specimens, and the average loop height and bonding strength (pull test ) was measured. These measurement results are also shown in Table 1. For the purpose of comparison, Table 1 also shows the test results of a thin Au wire having a diameter of 25 mmφ under the same conditions. As is clear from the results shown in Table 1, the hardness of the ball formed at the tip of the Pd thin wires 1 to 7 of the present invention is lower than 60, which is almost the same as that of the Au thin wire. Due to its hardness, during wire bonding, there is no rejection phenomenon in the aluminum pad part or damage phenomenon in the semiconductor element, and it also shows strong bonding strength and the loop height is as high as that of Au. It was hot. On the other hand, unrefined Pd thin wires whose purity and content of Pt and Fe as unavoidable impurities are outside the scope of the present invention all have ball hardnesses of 60 or more on the Vickers hardness scale. Therefore, when wire bonding is performed, aluminum pads are often rejected and semiconductor elements are damaged, and the high temperature strength is too high, resulting in low loop heights. As mentioned above, the Pd thin wire of the present invention has moderate high-temperature strength, so the loop height after wire bonding is high, and the hardness of the ball formed at the wire tip during wire bonding is also very high. Due to its low hardness of less than 60, it does not cause aluminum repulsion to the aluminum pad of the semiconductor element or damage to the semiconductor element itself.
Furthermore, it has industrially useful properties such as wire bonding that can be performed with high bonding strength.

Claims (1)

【特許請求の範囲】[Claims] １ 純度：99.995重量％以上のPdからなり、かつ
不可避不純物としてのPtおよびFeの含有量を、
それぞれ15ppm未満として、ワイヤ先端部に形成
されるボールの硬さをビツカース硬さで60未満と
したことを特徴とする半導体装置のワイヤ・ボン
デイング用Pd細線。1 Purity: Consisting of 99.995% by weight or more of Pd, and the content of Pt and Fe as inevitable impurities,
A fine Pd wire for wire bonding of semiconductor devices, characterized in that the hardness of the ball formed at the tip of the wire is less than 60 in terms of Vickers hardness.
JP58075334A 1983-04-28 1983-04-28 Pd fine wire for wire bonding of semiconductor device Granted JPS59201454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58075334A JPS59201454A (en) 1983-04-28 1983-04-28 Pd fine wire for wire bonding of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58075334A JPS59201454A (en) 1983-04-28 1983-04-28 Pd fine wire for wire bonding of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59201454A JPS59201454A (en) 1984-11-15
JPH0237698B2 true JPH0237698B2 (en) 1990-08-27

Family

ID=13573249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58075334A Granted JPS59201454A (en) 1983-04-28 1983-04-28 Pd fine wire for wire bonding of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59201454A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2873770B2 (en) * 1993-03-19 1999-03-24 新日本製鐵株式会社 Palladium fine wire for wire bonding of semiconductor devices
CN113241303A (en) * 2021-05-19 2021-08-10 合肥矽格玛应用材料有限公司 Packaging bonding platinum wire and preparation method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56169342A (en) * 1980-05-31 1981-12-26 Tanaka Kikinzoku Kogyo Kk Bonding wire for semiconductor element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56169342A (en) * 1980-05-31 1981-12-26 Tanaka Kikinzoku Kogyo Kk Bonding wire for semiconductor element

Also Published As

Publication number Publication date
JPS59201454A (en) 1984-11-15

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