JPS6378077A - Memory aging circuit - Google Patents

Abstract

PURPOSE:To simplify an equipment on a manufacturing line by incorporating a clock generating circuit, an aging pin, and an aging controlling circuit in a package, making an external signal unnecessary, and using an aging tank is common. CONSTITUTION:In a package which has been constituted so that a dynamic RAM 2 is controlled by a memory control part MMC 1 and brought to an access, a clock generating circuit, an aging pin and an aging controlling circuit are incorporated. In this state, a memory request signal is switched by AND circuits 4, 5 and an OR circuit 3, and a clock signal is switched by AND circuits 6, 7 and an OR circuit 8. Also, a control signal SND-N is provided as a package aging signal, and when a power source of +5V is fed to the package, the signal SND-N becomes a high level, the clock and memory request signals to the MMC 1 become ON, and a pseudo request shape is formed. The MMC 1 executes a memory access operation, irrespective of aging and other operation environments. In this way, aging can be executed by executing only a power source feed by the package unit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to aging at the level of a single package,
The present invention relates to an aging circuit that can unify aging tanks and is particularly suitable for aging dynamic memory.

[Conventional technology]

Conventional aging methods include a method in which a single element is assembled into a package after aging, and a method in which only the memory section is physically separated from the package and external logic is added to the aging device to perform aging under external control. The former method resulted in an increase in man-hours, and the latter method resulted in physical constraints and an increase in the number of aging devices, which caused the problem that production equipment could not keep up with the miniaturization of terminals. Known examples include JP-A-59-178696, JP-A-59-478697, and JP-A-59-227095.

[Problem J to be Solved by the Invention The above-mentioned prior art solves this problem by creating a structure in which the memory section is logically separated within the package, and by adopting a PK format suitable for an aging bath dedicated to dynamic memory. in this case,
This method connects the memory control unit and memory when the device is installed, which results in an increase in the number of input bins and limits the arrangement of input bins when used in other devices.

Furthermore, since the connection mechanism is not eliminated, a platter and a connection cable in place of the platter are required, making it impossible to reduce the size and price.

Other methods can be implemented without memory aging, but this is essential from the perspective of delivering more stable products.

An object of the present invention is to solve the above problems.

[Means for solving problems]

The above object is achieved by providing a clock generation circuit in the package and generating pseudo memory access signals from the clock generation circuit during aging to generate memory activation signals RAS and CAS.

To switch the operation, assign the aging pin to the input pin,
Normal oven (power supply status for single package)
It is output as a high level signal, and is low when the device is installed.
By using a W level signal, the logical clock generation circuit can operate only with power supply, and the memory control section can control memory access, so it can be operated using the same logic. The aging pin logically converts the clock signal into a clock signal for memory control and a pseudo memory access signal, allowing asynchronous operation without system operation, making the aging circuit simple. It can be operated only with

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of a package implementing the present invention.

A dynamic RAM 2 (abbreviated as D-RAM) is used as a groove bottom that is controlled and accessed by the memory control unit MMC1. For D-RAM, RAS-N is used as a control signal.
/CAS-N is a control signal that gives addresses in a time-division manner.

First, the operation contents of the package device will be explained.

When a μ-CPU (not shown) accesses the memory, it specifies the memory address with the CADR-N signal and RW-
The N signal instructs the memory read or write operation, and at the same time, the M signal is sent as the original operation request to the memory.
EQ-N is also turned on at the same time, and MM is set based on these signals.
Cl performs memory access operations. clock signal M
CLK-P is constantly supplied. Further, the 5ND-N signal is always given a LOW level to operate.

Next, the memory operation when aging this package will be explained.

A 5ND-N control signal is provided as a signal for package aging, and when used on the device, it is operated by giving a low level, but during aging operation, no signal is given from the outside, so that the noise level is fixed. To supply,
Leave it as a pull-up circuit.

When the package is powered with +5V power, 5ND-N
The signal becomes a high level signal, and the clock and memory request signals to M Mc are turned on, resulting in a pseudo request form. Regardless of aging or other operating environments, MMC
A memory access operation will be executed.

Clock supply can be achieved by incorporating the basic clock generation circuit part of the device into the same package. Switch the memory request signal with AND circuit 4.5 and OR circuit 3,
The clock signal is switched by the AND circuit 6.7 and the OR circuit 8, and the other signals are used as common signals.

FIG. 2 shows the m composition during package aging. Aging tank 13, aging package 12
and an external power supply 10 that supplies power to it.

The aging tank will be capable of inserting multiple packages and will have the ability to perform voltage margin and temperature margin tests.

As for the package operation function during aging, it is necessary to operate the on-board D-RAM only by power supply, and the D-RAM is simulated by X-TAL (which generates tarok signal only by power supply) inside the package. It is only necessary to operate the logic to be accessed.As a method for this, it is necessary to distinguish between operating without various control signals from outside the package and operating using external control signals.
The basic logic circuit that can perform the 5° pseudo operation using the control signal 5ND-N of the first path incorporates the #I logic formed by four gates shown in the 1M, and an address generation circuit inside the LSI.

When configured as a device, it operates from an external control signal, inputs the address from the CADR-N signal of Chiku1 Minami, and instructs read and write operations of D-R and AM with the RW-N signal. , MREQ-N signals indicate that there is a memory access request, and the MCLK-P signal performs timing control.

This operation is performed by an external controller such as a .mu.m CPU or the like to perform the aging operation described above.

Figure 3 shows the external control signal of the circuit shown in Figure 1.
This figure shows a time chart for accessing AM. In this case, the 5ND-N signal is at a low level, and the clock signal to the M IC is stopped by the AND gate 7.
and AND gate 4 and AND gate 5, the memory access signal is changed from MREQ-N to LS as it is.
Supplied to I. This circuit allows LSI MMC to access memory using an external control signal. 5ND again
By inputting the -H control signal MΔ(C), the internal address generation circuit can be accessed using the external signal CADR-N address signal.

Conversely, in aging mode operation (operation when SND-N is at high level), MREQ-N, MCLK
−P supply is stopped and the access signal is 5N instead.
The D-N signal is input as is, and the MMC operates as if memory access is being performed continuously.

The operation timing is determined by an external grinding clock.

It supplies the clock timing of the X-TAL output and enables operation. That is, in the time chart shown in FIG. 3, MREQ-N remains on and the address is M
The R and W-N signals that are automatically generated within the MC are fixed (read or write operations are fixed) and the 8ND-N signal state is internally supplied to the MMC. It is possible to make a farm.

〔Effect of the invention〕

According to the present invention, by only supplying power to a single package, aging can be performed more efficiently than dynamic RAM, and since external signals are not required, aging tanks can be shared and equipment on the manufacturing line can be simplified. can.

[Brief explanation of the drawing]

The first figure is a block diagram of the memory control section in a package showing an embodiment of the present invention. Figure 2 is a diagram for explaining the f11 configuration during pan cage aging. 3 is a time chart showing access to RAM using a control signal. 1...Memory control unit MMC, 2...Dynamic R
LAM 3...OR1 gate, 8
...OR gate.

Claims (1)

[Claims] 1. By incorporating a clock generation circuit, an aging pin, and an aging control circuit into a single package that includes memory, its control circuit, and other functional circuits, a special control signal can be applied from the outside to aging the memory. A memory aging circuit that is characterized by being capable of aging only by supplying power without operating it.