JPS6376186A - Control circuit for dual port ram - Google Patents

Abstract

PURPOSE:To eliminate the need for a complicated arbitrating circuit by completing a writing control in the sufficiently shorter time than a reading control, and removing the disturbance of the reading data due to the writing control operated at an arbitrary time with a smoothing means. CONSTITUTION:A waveform (e) of the shifting signal of data reading is added to a shifting signal input terminal 10 regardless of signals (a) and (b) of a writing control relation. By the front edge of the shifting signal waveform (e), a first counter 2 is counted up and the address information of the first counter 2 is added via an address switching circuit 4 as the reading address of a RAM 1. Since a part of an address (d) at the time of the writing control is mixed in a waveform (g) which is the address signal of the RAM 1, the data at the time of writing are mixed besides inherent reading data into a reading waveform (h) of the RAM 1. Since the part of the writing cycle is set sufficiently shorter than the reading cycle, the influence is removed by passing through an integrating circuit 8. As the result, a waveform (i) of the inherent reading data is given to an output terminal 9 of the RAM 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a two-port RAM control circuit, and more particularly to a two-port RAM control circuit that eliminates the need for an arbitration circuit that arbitrates simultaneous accesses from each port.

[Prior Art] Conventionally, a control circuit for a two-port RAM has been comprised of an address switching circuit that switches address information from two ports, and an arbitration circuit that arbitrates simultaneous accesses from the two ports. When accesses occur from two ports at the same time, the arbitration circuit waits for accesses from either port, and performs control to execute accesses separately for each port.

[Problems to be Solved] The conventional two-port RAM control circuit described above has a problem in that the arbitration circuit that arbitrates simultaneous accesses from two ports is extremely complex.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a two-port RAM control circuit that has a simple configuration and eliminates the need for a conventional complicated arbitration circuit.

[Means for solving the problem] In order to achieve the above object, the control circuit of the two-port RAM of the present invention has a structure in which the read-only port is equipped with a smoothing means and the write cycle is sufficiently short compared to the read cycle. be.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 shows a schematic configuration diagram of a control circuit for a two-port RAM according to an embodiment of the present invention. Note that this embodiment uses FIFO
operates as

In the figure, 1 is a RAM that stores data, 2 is a first counter that generates a read address based on address information from a read-only boat, and 3 is a first counter that generates a write address based on address information from a write-only boat. This is the second counter. Address output terminals of the first and second counters 2 and 3 are connected to an address input terminal of the RAM 1 via an address switching circuit 4. The address switching circuit 4 normally switches between the first counter 2
It is switched to the second counter 3 side only while there is a write request.

Reference numeral 5 denotes a write data input terminal, which is connected to the data input terminal of the RAM1. Reference numeral 6 designates an input terminal for a write control signal, which is connected to a count-up terminal of the second counter 3, a switching signal input terminal of the address switching circuit 4, and an input terminal of the timing adjustment circuit 7. The timing adjustment circuit 7 adjusts the RA based on the write control signal.
It generates a write pulse of M1, and its output terminal is connected to the write 1 terminal of RAM1.

Reference numeral 8 denotes an integrating circuit, and data read from the RAMI is outputted to a read data output terminal 9 via this integrating circuit 8. Reference numeral 10 denotes an input terminal for a data read shift signal, which is connected to the count-up terminal number of the first counter 2.

FIG. 2 shows an example of operating waveforms of the control circuit of the Nipport RAM shown in FIG. In FIG. 2, a to i indicate the waveforms of each part a to i in FIG.

In the above configuration, in order to write data, a write control waveform is applied to the write control signal input terminal 6 so as to punch out the write data waveform a.

At the front edge of this write control waveform, the second counter 3
At the same time, the address switching circuit 4 is switched to the second counter 3 side.

The timing adjustment circuit 7 generates a write pulse C and adds it to the RAM 1 after the output waveform d of the second counter 3 becomes stable and a certain period of time has elapsed. RAM1 receives this write pulse C and stores data at the designated write address. Note that the address switching circuit 4 is replaced by the second counter 3.
The time for switching to the side is sufficiently short compared to the read cycle.

On the other hand, the read port, including during this write control,
Always remain in read mode.

The waveform e of the data read shift signal is applied to the shift signal input terminal 10 regardless of the write control related signals a and b. Then, the first counter 2 is counted up by the pre-etch of this shift signal waveform e, and the first counter 2 is counted up.
address information is transferred to the RAM via the address switching circuit 4.
Add as read address 1.

Due to the read control as described above, the address signal of the RAM 1 has a waveform g. By the way, this waveform g includes a part of the address d during write control. Therefore, in the RAMI read waveform, write data is mixed in with the original read data. However, since this write cycle portion is set to be sufficiently shorter than the read cycle, this influence is removed by passing the signal through the integrating circuit 8. As a result, output terminal 9 of RAM1
is given the original read data waveform i.

In this embodiment, an integrating circuit is used as a smoothing means to remove the influence during write control, but the same effect can be obtained by using an averaging circuit or the like.

[Effects of the Invention] As explained above, the present invention allows write control to be completed in a sufficiently shorter time than read control, and uses a smoothing means to remove disturbances in read data due to write control performed at arbitrary times. This has the effect of eliminating the need for a complicated arbitration circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a control circuit of a two-port RAM according to an embodiment of the present invention, and FIG. 2 is a waveform diagram of each part of the circuit of FIG. l: RAM 4 Near address switching circuit 8: Integrating circuit

Claims (2)

[Claims] (1) A two-port RAM that has a write-only port and a read-only port, and uses an address switching circuit to selectively switch address information from each port and supply it to the RAM.
1. A control circuit for a two-port RAM, characterized in that the read-only port is equipped with a smoothing means, and the write cycle is sufficiently shorter than the read cycle. (2) A control circuit for a two-port RAM according to claim 1, wherein the smoothing means includes an integrating circuit.