JPS6089763A - Period measuring device - Google Patents

Abstract

PURPOSE:To measure the period of an input pulse continuously by operating counters of two systems alternately by switching, and storing measurement results in a memory. CONSTITUTION:An input X is inputted to an FF1, whose output Q is made into two frequency divided signals. Those two signals are gate signals for input clocks CLK to the counters 4 and 5. Pulses obtained by delay circuits 6 and 7 are inputted as a write signal to the memory 11 through an OR gate 8 and a switch 9. A data selector 12 selects the output of the counter 4 or 5 and inputs it to the data line of the memory 11. A control circuit 15 operates switches 9, 10, and 14 and controls the output of the data selector 12 according to a write and a read mode to generate a read signal RD and an address updata pulse INCR.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a period measuring device that can continuously measure the period of pulse input.

[Prior art]

There are cases where it is desired to continuously measure the period of a pulse input in real time, one period at a time. Until now, no period measuring device suitable for such a purpose has been found. For example, there is a period measuring device that uses a waveform storage device to measure the pulse period for each period, although it is not a real-time measurement.

This device uses a method of measuring and storing the input pulse waveform during a certain period of time, and then calculating the period from the stored data.

However, such devices have problems such as being expensive and requiring time to process data after storage.

[Purpose of the invention]

In view of these points, it is an object of the present invention to provide an inexpensive period measuring device that can continuously measure the period of input pulses in real time.

[Summary of the invention]

To achieve such an object, the present invention has two systems of period measurement counters, A and B, and the period of the input pulse is set to A and B.
By alternately switching between B, A, B, etc., and storing the count results of the other counter in the memory while one counter is measuring, it is possible to continuously measure the period of the input pulse. It is characterized by what it did.

〔Example〕

The present invention will be described in detail below using the drawings. FIG. 1 is a configuration diagram of main parts showing an embodiment of a period measuring device according to the present invention. Reference numeral 1 denotes an edge trigger type flip-flop which divides the frequency of the pulse input signal to be measured by two and outputs complementary outputs Q and Q. 4 is the first counter, 5 is the second counter,
The period measurement reference clock CLK (period sufficiently short compared to the pulse signal to be measured) that has passed through gate 2 and gate 3 is counted. The output of gate 2 is the AND of the Q output of flip-flop 1 and clock CLK, and the output of gate 3 is the AND of 6 outputs of flip-flop 1 and clock CLK.

Reference numerals 6 and 7 denote first and second delay circuits, each of which delays the falling edge of the Q output of the flip-flop 1. The two delayed pulses obtained by the delay circuits 6 and 7 are input to the OR gate 8.
The output is inputted to the memory 11 via the switch 9 as a write signal.

Furthermore, the signals after the delay pulses from the delay circuits 6 and 7 serve as clear signals for the counters 4 and 5, respectively.

A 12 company data selector selects the outputs of counters 4 and 5 and is connected to the input of the data line of memory 11.

For the input switching signal of the data selector 12, the 6 output signal of the flip 70 tube 1 is used.

The output of a memory address counter 13 is connected to the address line of the memory 11, and the input signal to be measured X is connected to the input of this counter 13 via a switch 14. The count value is updated each time the arrival occurs.

15 is a control circuit, which switches fl and 10 depending on the write mode and read mode; :Controls switching of L4 and output of data selector 12, and generates read signal RD and address update pulse INCR.

The operation in such a configuration will be explained next with reference to the time chart of FIG.

(1) Write mode input Become. These two signals serve as the gates for the input clock CLK of counters 4 and 5, respectively. As a result, the first counter 4 receives T1°T, T,...
.T2, T4' 5 T6. Count the period in the interval... The delay circuit 6 generates signals (signals C and E in FIG. 2) in which the fall of the Q output is delayed. The other delay circuit 7
is a signal (second
Create signals (a) and (s) in the figure. Here, to) and (
) is ORed at the gate 8, and the write signal W of the memory 11 is output.
It becomes R. In the write mode, switch 9 is ON, switch 10 is OFF, and switch 14 selects input X.

The signals from (to) and (I) are input as clear signals to each of the counters 4 and 5.

Counter 4 counts clock CLK in interval T1.

At this time, the counter 5 is in a clear state and no clock counting is performed. At the end of the T□ section, gate 2 closes and clock input is prohibited. On the other hand, the data selector 12 selects the output of the counter 4 based on the d output of the flip-flop P1 and guides it to the memory 11. Here, the counted value of the counter 4 is written into the memory 11 by the signal (2) (indicated in FIG. 2). The address of the memory at this time is the count value of the counter 13 that counted the input X. When the writing is completed, the counter 4 is cleared by a clear signal 0.) applied thereafter from the delay circuit 6, and the cleared state continues until the T3 period is entered.

On the other hand, the counter 5 starts counting the clock CLK input from the gate 3 at the same time as the start of the T2 period.

When the T period ends, the Q output of 7 lip-flop 1 becomes the second
Since the value becomes "0" as shown in (f) of the figure, clock input is prohibited and counting is stopped. At this time, the data selector 12
selects the output of counter 5 and sends it to the data input terminal of memory 1. The memory 1 stores the count value inputted from the WR multiplication signal shown in FIG. 2(a). In this case, the write address is the address in the T□ interval +1. When the writing is completed, the counter 5 is maintained in the clear state by the clear signal shown in FIG. 2(S) until the start of the J+'r period.

Thereafter, by repeating the same counting operation, the measured value of each cycle is stored in the updated address.

(2) After completing the read mode measurement, switch and switch 9 under the control of the control circuit 15.
is OFF, the N switch 10 is ON, and the switch 14 is switched to the control circuit side. At the same time, the control circuit 15 issues an output prohibition signal INHIBIT to the data selector 12 to open the data selector output terminal.

In this state, from the control circuit 15 to the counter 13
NCR is applied, a read signal RD is applied through the switch 10 while updating the address of the memory, and the measured count value (value corresponding to the period) is read out from the memory 11. Read data is sent to a predetermined device via a data bus 1G wired-OR coupled to a data line.

〔Effect of the invention〕

By alternately operating the two series of counters and storing the measurement results in memory, the period of the input pulse can be continuously measured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the period measuring device of the present invention, and FIG. 2 is an operational waveform diagram of each part. 1...Flip-flop, 4...First counter,
5... Second counter, 6... First delay circuit, 7... Second delay circuit, 2.3.8... Gate, 9,10° 14... Switch, 11 . . . memory, 12 . . . data selector, 13 . . . address counter, 15 . . . control circuit.

Claims (1)

[Claims] First and second gate means for passing a reference clock alternately every cycle of an input pulse signal, first and second counters for respectively counting the clocks from the gate means, and outputs of these two counters. a data selector that outputs the output data alternately and at once; a memory that stores the output data of the data selector and is capable of reading the stored data; and a memory that counts the input pulses or pulses from the control circuit. An address counter is provided for counting the address value of the memory, and when one of the two counters starts counting clocks, the count value of the other counter is written to the memory via a data selector, and after this writing, The counter that outputs the counted value is cleared, and when reading the stored counted value, the output of the data selector is prohibited, and the address counter is made to count read-only pulses to obtain the memory address. A period measuring device, characterized in that the period of the input pulse is continuously measured by reading out the count value for each period stored in the memory.