JPS6376043A - Data transfer system - Google Patents

Abstract

PURPOSE:To suppress the transfer of invalid data by allowing a direct memory access (DMA) control means receiving a command for temporarily stopping data transfer to stop the continuous transfer of the succeeding data group after ending the transfer of a transferring data group. CONSTITUTION:Receiving a temporary stop command of data transfer from a data transfer stop commanding means 300 in a processor 1 during the continuous transfer of plural data groups 100 by a DMA control means 200, a data transfer stopping means 400 ends the transfer of a transferring data group 100 and then stops the continuous transfer of the succeeding data group 100. Thereby, only the complete data group 100 is transferred before the stop of the transfer. Consequently, all the transferred data are validated and the transfer of invalid data can be suppressed.

Description

[Detailed Description of the Invention] [Summary] In an information processing system having a direct memory access system, an instruction to temporarily stop data transfer is transmitted from a processor to a direct memory access control means, and the instruction is received. After the direct memory access control means finishes transferring the data group being transferred, it stops continuous transfer of subsequent data groups, thereby making it possible to prevent invalid data from being transferred.

[Industrial application field]

The present invention relates to an improvement in a data transfer abort method in an information processing system having direct memory access control means.

2. Description of the Related Art In information processing systems, a direct memory access control function that transfers data stored in a memory to an input/output device or the like without imposing a load on a processor is widely employed.

In such an information processing system, when data transfer is temporarily stopped during continuous transfer of a plurality of data groups stored in memory, only a part of the data groups is prevented from being transferred and becoming invalid. It is hoped that the means will be provided.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional data transfer method in this type of information processing system.

In FIG. 3, three data groups (hereinafter referred to as frames F1 to F3) each having a data amount f1 to f3 are stored in areas 41 to 44 having a predetermined storage capacity iB in the memory 4.

Data tfl and f3 of frames F1 and F3 are
Since both have less than the storage capacity B, they are stored in separate areas 41 and 44, respectively. However, since the data of frame F2 @f2 has more than the storage capacity B, each has a storage capacity MB.
It is divided into subframes SF2 and SF3 having the following data amounts sf2 and sf3, and areas 42 and 4
It is stored in 3. It is assumed that the frames F1 to F3 have meaning only when the total data amounts r1 to f3, respectively, are complete.

When sequentially transferring frames F1 to F3 to the input/output device 2, the processor 1 transfers the frames F1 to F3 to the area 45 in the memory 4.
to 48 are various information groups (hereinafter referred to as command disc libter D) that define data transfer operations in each area 41 to 44.
PI to DP4) are set, and the command disc libter DPI corresponding to the frame F1 to be transferred first is set in the internal register 31 provided in the direct memory access control device 3 (hereinafter referred to as the DMA control device 3).
After setting the start address ao1, start up.

Each command disc libter DPI to DP4 contains the start address ah of the corresponding areas 41 to 44, the data lb stored in the areas 41 to 44, and the data in other areas following the data in the corresponding area. Chain information 11cE indicating whether to transfer or not (logical “1” in case of continuous transfer,
(Logic “0” in case of non-continuous transfer) and W! indicating whether the data in the corresponding area is a frame or a subframe. If the chain information CE is set to logic "0" for a DCC frame and logic "1" for a subframe), and the chain information CE is set to logic "1", it corresponds to other subframes that make up the same frame. The first address (next address an) of the command disc libter is included.

In FIG. 3, in order to continuously send out frames F1 to F3, command disc libters DP1 to DP3 are used.
The chain information CE of both are set to logical "1", and the start address a02 of the storage areas 46 to 48 of the command disk libters DP2 to DP4 is set as the next address an, respectively.
A04 to a04 are stored, and the command disk libter D
The chain information 91CE of P4 is set to logic "0".

Also, since the data in areas 41 and 44 are frames F1 and F3, respectively, the command disc libter DP
The 'm connections igDc of I and DP4 are both set to logic "O", and the data in areas 42 and 43 are in subframes SF2 and SF3 constituting the same frame F2.
Therefore, the command disc libters DP2 and DP3
41! Continuation information DC is logic “1” and logic “, respectively.
0”.

The DMA control device 3 started by the processor 1 reads the command disk libter D stored at address a01.
From PI to start address ah=all and data amount b=
After extracting fl and setting it in the internal register 31 as transfer data address at and transfer data lbt, data in frame Fl is sequentially extracted from address all and transferred to the input/output device 2, and the data is set as transfer data address at and transfer data lbt.
"1" is sequentially added to the transfer data lbt, and "1" is subtracted sequentially from the transfer data lbt.

The transfer of frame F1 is completed, and the transfer data lbt is “0”.
”, the DMA control device 3 stores the transfer end information in the command disk libter DPI, then refers to the chain information CE, and when it identifies it as logic “1”, transfers the next address a n from the command disk libter DPI. =a 02
is extracted and stored in the internal register 31.

Thereafter, the DMA control device 3 controls the frame F based on the command descriptor DP2 stored at the address a02.
2 transfer starts.

Thereafter, the DMA control device 3 transfers frames F1 to F3 in the same manner.

In such a state, while the DMA control device 3 is transferring the frame F1, the processor 1 sends an instruction from the processor 1 in order to change the transfer order of frames F2 and F3, or to stop the continuous transfer of frames F3, etc. When a transfer stop command to temporarily stop data transfer is transmitted to the DMA control device 3, the DMA control device 3 stops transferring the frame F1 upon receiving the transfer stop command.

As a result, only part of the frame F1 is transferred to the input/output device 2, so the transferred data has no meaning.

It becomes something you don't want.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in a conventional data transfer method, the DMA control device 3 controls the frames F1 to F3.
When a transfer stop command is received from the processor 1 while continuously transferring frames, the frame transfer is immediately stopped at the time of reception.

Therefore, only part of the frame will be transferred, and the transferred data will also be invalid.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 1 represents a processor, 100 represents a data group, and 200 represents a direct memory access control means.

Reference numeral 300 denotes data transfer stop instruction means provided in the processor (1) according to the present invention.

Reference numeral 400 denotes data transfer stop means provided in the direct memory access control means 200 according to the present invention.

[Effect]

The data transfer aborting means 400 is configured to stop the data transfer instructing means 30 in the processor 1 while the direct memory access control means 200 is continuously transferring a plurality of data groups 1°O.
When a data transfer temporary stop instruction is received from 0, after the data group 1°O being transferred is completed, continuous transfer of the subsequent data group 100 is stopped.

Therefore, before the transfer is stopped, only a complete data group 1°O has been transferred, all of the transferred data becomes meaningful, and invalid data is prevented from being transferred.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a data transfer method according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, a cancel instruction setting section 1 is provided in the processor 1.
1 is provided as a data transfer abort instruction means 300, and a transfer abort section 32 is provided in the DMA control device 3 as a data transfer abort means 400.

In FIG. 2 as well, areas 41 to 44 in the memory 4 contain frame F1, subframes SF2 and SF3 constituting frame F2, and frame F3.
are stored, and each area 41 is stored in areas 45 to 48.
Command disc libters DPI to DP4 that specify the transfer of data in frames F to F44 are stored.
It is specified that 1 to F3 are sent out consecutively.

In FIG. 2, while the DMA control device 3 is transferring frame F1, the processor 1 transfers frames F1 to F3 in order to change the transfer order of frames F2 and F3, or to stop continuous transfer of frame F3. When it becomes necessary to temporarily stop the continuous transfer of data, the stop instruction setting section 11 in the processor 1 is activated.

The suspension instruction setting unit 11 transmits a transfer temporary suspension command to the DMA control device 3 and sets transfer temporary suspension information isP in the internal register 31.

When the DMA control device 3 identifies that the transfer temporary suspension information flsP has been set in the internal register 31, it activates the transfer suspension unit 32.

The transfer canceling unit 32 refers to the transfer data ibt set in the internal register 31, and determines whether the transfer data ibt is “0”.
”, the DMA controller 3 continues to transfer the frame F1 based on the transfer data address at and transfer data lbt set in the internal register 31, and monitors the transfer data amount bt.

Upon identifying that the transfer data lbt has become rOJ, the transfer aborting unit 32 further refers to the continuation information DC set in the internal register 31 and confirms that it is set to logic "0". It is determined that the transfer of frame F1 has been completed, and the DMA control device 3 is made to temporarily stop the transfer of frame F2 and subsequent frames.

As a result, the frame F1 has been completely transferred to the input/output device 2, and the frame F1 is determined to be valid.

As is clear from the above description, according to this embodiment, the DM
Even if the processor 1 transmits a transfer suspension command while the A control device 3 is continuously transferring frames F1 to F3, the transfer will be temporarily suspended after all frames F1 being transferred are completed. It becomes possible for the input/output device 2 to determine that the transferred frame F1 is valid.

Note that FIG. 2 is only one embodiment of the present invention, and for example, the number of frames that are continuously transferred and the amount of data in each frame are not limited to what is shown in the figure, and many other modifications may be made. However, the effects of the present invention remain the same in either case. Furthermore, the configurations of the command disc libters DPI to DP3 are not limited to those shown in the drawings,
Although many other modifications may be considered, the effects of the present invention remain the same in any case.

〔Effect of the invention〕

As described above, according to the present invention, in the information processing system, a complete data group has been transferred before the transfer is stopped, all the transferred data becomes meaningful, and invalid data is prevented from being transferred.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a data transfer method according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional data transfer method. In the figure, 1 is a processor, 2 is an input/output device, and 3 is a D
M A control device, 4 a memory, fl an abort instruction setting unit, 31 an internal register, 32 a transfer abort unit, 41 to 4
8 is an area, ioo is a data group, 200 is a direct memory access control means, 3゜O is a data transfer stop instruction means, 400 is a data transfer (, ChijP, between 1st mouth Jζ also in August and 7th middle ■d-b "j(. 2nd figure f-plexus δ filter tenitor yoke CL method % formula %

Claims (1)

[Scope of Claims] In an information processing system comprising a direct memory access control means (200) having a function of successively transferring a plurality of data groups (100), a processor (1) is provided with a direct memory access control means (200). Data transfer stop instruction means (3) transmits an instruction to temporarily stop the data transfer to the direct memory access control means (200) after the data group (100) being transferred is completed by the data transfer control means (200).
00), and the direct memory access control means (200) includes:
Data transfer in which, when the temporary stop instruction is received during continuous transfer of the data group (100), the continuous transfer of the subsequent data group (100) is stopped after the transfer of the data group (100) being transferred is completed. A data transfer method characterized by providing a stop means (400).