JPH0421896B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transfer control method, particularly a data transfer control method that controls data transmission/reception between a data processing system and a terminal device, or between a terminal device and a terminal device. It is related to the method.

[Conventional technology]

In data transfer between a data processing system and a terminal device such as a workstation, a response frame acknowledging receipt of an information frame is generally transmitted when software processes the information frame.

Normally, the other party (terminal device) starts transmitting the next information frame after receiving the response frame, so the above method cannot fully utilize the high-speed transfer capability of the terminal device. Therefore, in order to achieve high-speed transfer, when an information frame is received, a response frame may be returned at the firmware level before moving on to software-level processing, but in this case, the processing of the received information frame is The firmware may not be able to recognize when the software is processing, and as a result, when the next information frame is received from the other party, there is a risk that the storage area for information frames that have not yet been processed by the software may be destroyed. .

To avoid this, it is possible to provide multiple storage areas for information frames, but the response frame processing by the firmware and the information frame reception processing by the software cannot be synchronized, and the buffer is too large for high-speed data transfer processing. A situation may arise where no matter how many there are, they are insufficient.

[Problem that the invention seeks to solve]

The object of the present invention is to eliminate the above-mentioned conventional drawbacks and to
A plurality of data buffers for storing information frames are provided, thereby providing flexibility within the capacity (number) of these data buffers between the receiving processing of the sending processing firmware of the other party and the receiving processing of the software. This provides a more efficient data transfer control method.

[Means for solving problems]

In the method of the present invention, in data transfer control between a microprogram-controlled data processing system and a terminal device, confirmation of data arrival between the data processing system and the terminal device is received by the data processing system that has received the information frame. A data transfer control method that synchronizes data transfer by transmitting a confirmation frame to the terminal device, wherein the data processing system includes a plurality of data buffers for storing information frames sent from the terminal device; a busy/free identifier stored in an entry provided in the same number as a plurality of data buffers and indicating the busy/free state of the corresponding buffer; and a busy/free identifier stored in the entry and pointing to the address of the corresponding buffer. and a first and second entry pointer pointing to one of the entries, and upon receiving an information frame from the terminal device, transfers the information frame to the first entry pointer under microprogram control.
transfers and stores in the data buffer pointed to by the buffer address pointer in the entry pointed to by the entry pointer, sets the identifier in the entry to a busy state, and determines whether the identifier in the next entry is busy or free. Thereby, it is determined whether or not to transmit the reception confirmation frame to the terminal device and whether or not the first entry pointer can be updated, and the processing by the software of the information frame transferred and stored in one of the data buffers is determined. The firmware controls resetting the identifier in the entry pointed to by the second entry pointer to a free state and updating the second entry pointer by a software command issued upon completion.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment uses arithmetic processing unit 1 (hereinafter referred to as EPU).
1), an input/output control device 2 (hereinafter referred to as IOP2), and a main storage device 3 (hereinafter referred to as MMU) in which a buffer area 30 is set.
3) are connected via a common system bus 1000, and furthermore, as shown in FIG. -n (hereafter WS4-1
~WS4-n).

Figure 2 shows details of this IOP2. The IOP 2 is a microprogram-controlled input/output control device, and includes a microprogram execution control section 22, a system bus control section 23, and a local memory 24.
It is connected to the corresponding WS 4 via an input/output port 21 including a data transfer control section 25 .

FIG. 3 shows various parameters set in the local memory 24 in the IOP 2 for controlling data transfer. These are write entry pointers 2
41, read entry pointer 242, busy/
Free identifiers 243-1 to 243-4, data transfer lengths 244-1 to 244-4, and buffer address pointers 245-1 to 245
Contains -4.

In this embodiment, the buffer area 3 of MMU 3
As shown in FIG. 3, these parameters are divided into four entries and stored in correspondence with the four data buffers provided in 0. For example, the first entry contains a busy/free identifier. 243-1, length 244-1, and buffer address pointer 245-1 are stored, and these are parameters that hold information regarding the first data buffer provided in the buffer area 30 in the MMU 3. The same is true.
The write entry pointer 241 and the read entry pointer 242 each point to one of these four entries,
This is a pointer whose contents (the number of the entry it points to) are updated according to an algorithm that will be described later. Setting and updating of the values of these various parameters are processed by a microprogram running within the IOP2.

The local memory 24 is also used as a work area for this microprogram.

Now, the operation of this embodiment is as follows.

The EPU 1 reads and executes a software instruction in the MMU 3, and if the instruction is an input/output instruction (hereinafter referred to as an I/O instruction), it issues an I/O instruction to a designated IOP 2. I/O commands issued from EPU1 are sent via system bus 1000.
It is transmitted to the system bus control unit 23 of IOP2,
It is interpreted by the microinstruction execution control unit 22 of the IOP 2 and processed by executing the corresponding microprogram.

Now, a detailed description will be given of the processing when this data processing apparatus receives information frames irregularly transmitted from, for example, the work station WS4-1.

When the system is started up, various parameters set in the local memory 24 of the IOP 2 described above are initialized as follows by an I/O command issued from the EPU 1. That is, the busy/free identifiers 243-1 to 243-4 are all initialized to "0" in the free state, and each buffer address pointer 245-1 to 245-4 is provided in the buffer area 30 of the MMU 3. The write entry pointer 241 and the read entry pointer 242 are both set to point to the corresponding data buffer of the first entry (that is, the busy/free identifier 243-
1, length 244-1, and buffer address pointer 245-1).

Now, receive the information frame from WS4-1.
When the microprogram execution control unit 22 in the IOP2 recognizes the input data processing microprogram in the IOP2, the current write entry pointer 24
Instructs the data transfer control unit 25 in the input/output port 21-1 to transfer and store the received information frame to the data buffer in the MMU 3 pointed to by the buffer address pointer 245 of the entry pointed to by 1. The busy/free identifier 243 of this entry is set to "1", that is, the busy state, and then the busy/free status of the identifier 243 of the entry next to the entry pointed to by the current write entry pointer 241 is determined. And if this identifier 243 is “0”
That is, if it is in a free state, it issues an instruction to the input/output port 21-1 to send a response frame to WS4-1, and then points the write entry point 241 to the next entry. (Each entry has an endless configuration, and the fourth entry is updated to point to the first entry.)

Also, the identifier of the next entry at the moment is 24
If 3 is "1", that is, indicates a busy state, the response frame is not transmitted and the write entry pointer 241 is not updated.

In this way, when the identifier 243 of the next entry indicates free, a response frame is sent at the firmware level without waiting for processing by the software, and the other party that receives it has data to send. and immediately sends the next information frame, and when this information frame is received, it is sent to the MMU pointed to by the buffer address pointer of the next entry marked as free.
The data is transferred and stored in the data buffer No. 3. Thus, while the next entry's identifier 243 is designated as free, each time an information frame is received from the other party, regardless of software processing, a response frame is immediately returned to prompt the next transmission, and the other party It is possible to fully utilize the data transfer capability of the side.

Note that when the information frame is received, the next eletri identifier 243 is busy, so the response frame is returned and the write entry pointer 24 is busy.
1 is not updated, wait until the next entry's identifier 243 changes from busy to free, and when this change occurs,
Response frame return and write entry pointer 24
1 update.

On the other hand, these information frames received and stored in the data buffer provided in the buffer area 30 of the MMU 3 are processed by software.
Synchronization between this software processing and the firmware processing described above is performed as follows.

First of all, when the identifier 243 of the entry pointed to by the read entry pointer 242 changes to busy due to the reception and storage of an information frame as described above, the microprogram reads this entry in the buffer area 30 of the MMU 3. The information frame stored in the data buffer pointed to by the buffer address pointer 245 is transferred to the software area, and an interrupt is issued to the software to end the transfer.

When the software accepts this interrupt and finishes processing the information frame transferred to this software area, it is ready to read the next data.
Issue a READ command to IOP2.

When this READ command is received, the microprogram in IOP2 stores the current read entry pointer 24.
In response to the completion of processing of the information frame stored in the data buffer of MMU 3 pointed to by the buffer address pointer 245 of the entry indicated by 2, the identifier 243 of this entry is cleared to "0" and the read entry pointer 24
2 to indicate the next entry, and determine whether the identifier of this updated entry is busy or free. If this is busy, the information frame stored in the data buffer in the buffer area 30 of MMU3 pointed to by the buffer address pointer 245 of this entry is transferred to the software area, and the software is notified of the end of the transfer. Interrupt.

If the identifier 243 of this entry is "0", that is, free, then
Wait until this identifier 243 becomes busy, and at that point, as described above, read the information frame stored in the data buffer in the buffer area 30 of the MMU 3 pointed to by the buffer address pointer 245 of this entry. The data is transferred to the software area and a transfer end interrupt is generated to the software.

The software that received the interrupt processes the information frame transferred to the software area, and each time this processing is completed, a READ command is issued, and the microprogram that receives this READ command stores the current read entry pointer. 242
Set the identifier 243 of the entry pointed to by “0”
is cleared to update the read entry pointer 242 to point to the next entry, determine whether the identifier 243 of this updated entry is busy or free, and if it is "1", that is, busy, the entry pointer 242 of this entry is cleared. Buffer area 30 of MMU 3 pointed to by buffer address pointer 245
The information frame stored in the internal data buffer is transferred to the software area and a transfer completion report is made. Identifier 2 of the updated entry
If 43 is "0", the same processing as described above is performed after waiting until it becomes "1".

In this way, the synchronization between the software and the firmware is maintained, and the information frame that receives the transfer completion report is processed as quickly as the software allows, and when the processing is completed, a READ command is issued for the next information frame to be processed. However, when the firmware receives the READ command, it uses the identifier 243 of the entry corresponding to the buffer for which processing has been completed this time.
is cleared to 0'', and it is determined whether there is already an information frame to be processed in the next buffer (that is, the read entry pointer 242 is updated, and the identifier 243 of the entry pointed to by the updated entry pointer 242 is If the received data already exists in the buffer, it immediately transfers it to the software area and issues a transfer end interrupt to the software. If the data to be processed has not yet been received and stored in the buffer, wait for this reception and storage to occur (that is, wait for the identifier 243 of this new entry to change from "0" to "1"). ) Execute the above processing.

Thus, the software continues processing one information frame after another as long as there are information frames received as fast as it will allow, while the firmware is independent of the software processing as long as there is enough data buffer in the buffer area 30. Each time an information frame is received, it is stored in the data buffer and a response frame is returned to prompt transmission from the other party.

Thus, there is a buffer area 3 between the other party's transmission, firmware processing, and software processing.
Synchronization is performed with flexibility within the range allowed by the number of data buffers provided in the data buffer 0, and a data transfer system that operates with the highest efficiency can be realized.

Note that the above is an example of the present invention, and the present invention is not limited to the above example.

For example, in the embodiment described above, the number of data buffers is four, but this is merely an example.

Further, in the above embodiment, the identifier 24 pointed to by the updated read entry pointer 242
3 is "1", the firmware transfers the information frame stored in the data buffer pointed to by the buffer address pointer 245 of this entry to the software area, and issues an interrupt to the software to end the transfer. However, instead of this, the updated read entry pointer 24
If the identifier 243 indicated by 2 is "1", the firmware immediately interrupts the software, uses this interrupt to notify the software of the contents of the buffer address pointer 245 of this entry, The actual transfer of the information frame stored in this data buffer to the software area and the subsequent processing may be performed by software. In other words, the software issues a READ command after completing this process, but this
Upon receiving the READ command, the firmware clears the identifier of the entry pointed to by the current read entry pointer 242 to "0", updates the read entry pointer 242 to point to the next entry, and updates the read entry pointer 242 to point to the next entry. When the identifier 243 is "1", an interrupt is made to the software as described above, and the contents of the buffer address pointer 245 of this entry are notified to the software by this interrupt. If the identifier 243 of the updated entry is "0", wait until it becomes "1" and interrupt the software, and this interrupt will cause the buffer address pointer 245 of this entry to change. Notify the software of the content. In this way, the transfer from the data buffer to the software area can also be performed by software.

〔Effect of the invention〕

As described above, according to the present invention, in data transfer control between a microprogram-controlled data processing system and a terminal device, when the firmware of the input/output control device of the data processing system recognizes reception of an information frame, Rather than returning a response frame to a condition, this firmware has multiple data buffers for storing information frames and immediately returns a response frame regardless of software processing while there is another empty buffer;
Only when it is unavoidable because there is not enough room in the data buffer, synchronization is achieved by making the return of the response frame wait until the software finishes processing the received frame currently being processed.
As a result, synchronization is performed with flexibility within the range allowed by the number of data buffers between the transmission processing, firmware reception processing, and software reception processing of the other party, and the subsequent transfer of information frames is performed. Until the software processing cannot be completed in time and there is no more room in the data buffer, data transfer is achieved at the highest speed that can be achieved by the transmission data processing on the terminal device side and the firmware reception processing on the data processing system side. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing details of the input/output control device of this embodiment, and FIG. 3 is a diagram showing various parameters and pointers set in the local memory of the input/output control device. In the figure, 1... Arithmetic processing unit (EPU), 2
... Input/output control unit (IOP), 3... Main memory unit (MMU), 4,4-1 to 4-n... Terminal device (WS), 21-1 to 21-n... Input/output port,
22...Microprogram execution control unit, 23...
...System bus control unit, 24...Local memory, 25...Data transfer control unit, 30...Buffer area, 241...Write entry pointer, 24
2...Read entry pointer, 243-1 to 2
43-4...Busy/free identifier, 244-1
~244-4...Data transfer length (length), 2
45-1 to 245-4... Buffer address pointer.

Claims (1)

[Scope of Claims] 1. In data transfer control between a microprogram-controlled data processing system and a terminal device, confirmation of data arrival between the data processing system and the terminal device is performed by the data processing system that has received the information frame. A data transfer control method that synchronizes data transfer by transmitting a reception confirmation frame to the terminal device, wherein the data processing system includes a plurality of data buffers for storing information frames sent from the terminal device; A busy/free identifier stored in an entry provided in the same number as the plurality of data buffers and indicating the busy/free state of the corresponding buffer, and a busy/free identifier stored in the entry and pointing to the address of the corresponding buffer. a buffer address pointer and two first and second entry pointers pointing to one of the entries, and upon receiving an information frame from the terminal device, transfers the information frame to the first entry pointer under microprogram control.
transfers and stores in the data buffer pointed to by the buffer address pointer in the entry pointed to by the entry point, sets the identifier in the entry to a busy state, and determines whether the identifier in the next entry is busy or free. Thereby, it is determined whether or not to transmit the reception confirmation frame to the terminal device and whether or not the first entry pointer can be updated, and the processing by the software of the information frame transferred and stored in one of the data buffers is determined. The firmware controls resetting the identifier in the entry pointed to by the second entry pointer to a free state and updating the second entry pointer according to a software command issued upon termination. A data transfer control method characterized by: