JPS5955528A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS5955528A
JPS5955528A JP57166073A JP16607382A JPS5955528A JP S5955528 A JPS5955528 A JP S5955528A JP 57166073 A JP57166073 A JP 57166073A JP 16607382 A JP16607382 A JP 16607382A JP S5955528 A JPS5955528 A JP S5955528A
Authority
JP
Japan
Prior art keywords
data
host
length
received
received data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57166073A
Other languages
Japanese (ja)
Other versions
JPS6360428B2 (en
Inventor
Hitoshi Toyama
遠山 均
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57166073A priority Critical patent/JPS5955528A/en
Publication of JPS5955528A publication Critical patent/JPS5955528A/en
Publication of JPS6360428B2 publication Critical patent/JPS6360428B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To simplify the processing as well as to decrease the number of instructions between host communication controllers, by providing a means which informs the length of each reception data divided into one or plural blocks. CONSTITUTION:A reception data length holding means, etc. is provided to inform the length of each reception data divided into one or plural blocks. For instance, when the data is received at a host 1 from a terminal 5, the host 1 delivers a read instruction to a communication controller 2. Then the controller 2 performs transmission/reception via a transfer buffer 9, and a data length register 8 holds temporarily the count value of the length of the data which is transferred by a read command and then transfers the count value to the host 1 at the start of the data transfer. Then the data is transferred to a reception data buffer 6 of the host 1 from the buffer 9 via a data address register 10, etc. and in order of address rising.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、通信制御装置における受信データ長およびそ
のデータの転送方式に関し、特にハイレベル手順のよう
にデータ中にその終了を示すデリミタがなく、ホストが
受信データバッファをチェックしただけでは、その有効
データ長が分らない通信方式において、有効データ長を
ホストへ通知することを可能とするデータ転送方式に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to the length of received data in a communication control device and the transfer method of that data, and in particular, unlike high-level procedures, there is no delimiter in the data to indicate the end of the data. The present invention relates to a data transfer method that makes it possible to notify the host of the effective data length in a communication method where the effective data length cannot be determined just by the host checking the received data buffer.

〔従来技術と問題点〕[Conventional technology and problems]

従来、通信制御装置からホストへ、受信データ長をデー
タとして通知する方式には、 ■ 受信デ′−夕が格納されているバッファの先頭に、
該データ長を格納する。
Conventionally, the method for notifying the received data length as data from the communication control device to the host includes: ■ At the beginning of the buffer in which the received data is stored,
Store the data length.

■ 受信データが格納されているエリアの次のREAD
指令で示されるエリアに該データ長を格納する。
■ Next READ of the area where received data is stored
The data length is stored in the area indicated by the command.

02つの方式があるが、前者については、各ブロツクの
受信データの受信処理が完了してからでしか分らないデ
ータ長を、該データの前に格納しなけれはならないため
に、通信制御装置において、転送アドレスを該指令が示
すアドレスにもどす等の操作が必要となり、そのため処
理が複雑になるという欠点があった。一方後者について
は、1つのデータを受信するために2つのREAD指令
が必要となり、通信制御装置及びチャネルに負荷がかか
るという欠点があった。
There are two methods, but in the former, the data length, which can only be known after the reception processing of the received data of each block is completed, must be stored before the data. This requires operations such as returning the transfer address to the address indicated by the command, which has the disadvantage of complicating the process. On the other hand, the latter has the disadvantage that two READ commands are required to receive one data, which places a load on the communication control device and channel.

〔発明の目的および構成〕[Object and structure of the invention]

本発明の目的ti1、上記した従来方式の欠点全改良す
ることにあり、1つのREAD指令にコニリ、転送デー
タケ、そのデータ長もデータの1つとして含めて、該指
令で示されるホスト内受信データバッファのデータアド
レスの若番から昇順に格納することにより、処理の簡素
化全図り、特に、(n−1)番目のデータ長とn番目の
受信データをn th目のREAD指令で処理すること
によジ、ホストと通信制御装置との間のインタラクショ
ンの減少を==r能とするものである。
The purpose of the present invention is to improve all of the drawbacks of the conventional method described above, and to include the transfer data, the data length, and the data length in one READ command as one of the data, so that the received data in the host indicated by the command is By storing data addresses in the buffer in ascending order from the smallest number, processing can be simplified, in particular, the (n-1)th data length and the nth received data can be processed with the nth READ command. This reduces the number of interactions between the host and the communication control device.

本発F!Aは、そのための構成として、ホストからの指
令にもとづき動作する通信制御装置において、回線から
受信する一連または複数のブロックに分割されている受
信データのそれぞれのデータ長をホストに通知するため
の受信データ長保持手段をそなえ、n番目の受信データ
をホスト内に設けられた受信データバッファへ転送する
ためのホストからのREAD指令をRE A D # 
nとしたとき、ggEAD#n指令で示される上記メモ
リのデータ格納アドレスに、(n−1)番目に受信した
受信データのデータ長を上記受信データ長保持手段から
転送して先に格納し、その後上記データ格納アドレスに
続くアドレスにn番目に受信した受信データを順次格納
することにより、データ回線からの受信データおよびそ
のデータ長ケポストに転送することを特徴とするもので
ある。
Original F! For this purpose, A is a communication control device that operates based on commands from the host, and is configured to receive data received from a line and is divided into a series or a plurality of blocks, and to notify the host of the data length of each piece of data. It is equipped with a data length holding means and receives a READ command from the host to transfer the nth received data to the receive data buffer provided in the host.
n, the data length of the (n-1)th received data is transferred from the received data length holding means and stored first in the data storage address of the memory indicated by the ggEAD#n command; Thereafter, by sequentially storing the n-th received data in the address following the data storage address, the received data from the data line and its data length are transferred to the post.

〔発明の実施ρυ〕[Practice of the invention ρυ]

以下に、本発明を実施例にし/Cがって説明する。 The present invention will be explained below with reference to Examples.

第1図は、本発明実′MMFioのデータ通(Mシステ
ムの構成図である。同図において、1はホスト、2は通
信制御装置趙、3および4はモデム、5は端末、6は受
信データバッファ、7は制御部、8はデータ長レジスタ
、9は転送バッファ、1oは受信データバッファ6に対
するデルタアドレスレジスタを表わしている。
FIG. 1 is a block diagram of the data communication (M system) of the present invention MMFio. In the figure, 1 is a host, 2 is a communication control device, 3 and 4 are modems, 5 is a terminal, 6 is a receiver 7 is a data buffer, 8 is a data length register, 9 is a transfer buffer, and 1o is a delta address register for the reception data buffer 6.

ホスト1は、端末5がらデータを受信する場合、通信制
御装M2へREAI)指令を発行する。91っ(7J 
RE A D指令で転送されるデータのザイズはある一
定の上限内で任意であり、通信制御装置2において、転
送バッファ9を介して送受される。データ長レジスタ8
は、1つのREAD指令で転送されるデータの長さのカ
ウント値を一時的に保持し、次にhe < RE A 
D指令でのデータ転送の最初しこ、ホスト1へ転送され
る。転送バッファ9がらホスト1の受信データバッファ
6へのデータ転送処理は、アドレスの昇順にのみ行なわ
れ、データアドレスレジスタ1oにょシ管理される。デ
ータアドレスレジスタloは、ホストからのREAD指
令により開始アドレスを設定された後は、データ格納ア
ドレスを昇順に発生すれはよいため制御機構を簡単なも
ので済ますことができる。
When receiving data from the terminal 5, the host 1 issues a REAI) command to the communication control device M2. 91 (7J
The size of the data transferred by the RE A D command is arbitrary within a certain upper limit, and is sent and received in the communication control device 2 via the transfer buffer 9. Data length register 8
temporarily holds a count value of the length of data transferred in one READ command, then he < RE A
The first data transfer with the D command is transferred to the host 1. Data transfer processing from the transfer buffer 9 to the reception data buffer 6 of the host 1 is performed only in ascending order of addresses, and is managed by the data address register 1o. After the data address register lo is set with a start address by a READ command from the host, data storage addresses can be generated in ascending order, so that a simple control mechanism can be used.

第2図は、順次のRE A D指令における受信デルタ
バッファ6の内容を示したものである。
FIG. 2 shows the contents of the receive delta buffer 6 in sequential RE A D commands.

第3図は、各READ指令毎の受信データバッファ6に
おける受信データおよびデータ長さの格納動作の説明図
である○ 第4図は、1つのREAD指令について、制御部7が行
なう制御動作のフロー図である。
FIG. 3 is an explanatory diagram of the operation of storing received data and data length in the received data buffer 6 for each READ command. ○ FIG. 4 is a flowchart of the control operation performed by the control unit 7 for one READ command. It is a diagram.

以下に、第2図乃至第4図を参照して、実施例の動作を
説明する。
The operation of the embodiment will be described below with reference to FIGS. 2 to 4.

ホストが発行した最初のRE A D指令(#1)に対
して、通信制御装置は、直前にデータが存在しないため
に、受信データパツンア6のデータ長格納用エリアには
、ダミーキャラクタを格納する。
In response to the first RE A D command (#1) issued by the host, the communication control device stores a dummy character in the data length storage area of the received data patterner 6 because there is no data immediately before.

その後、受信データ#lを最後まで昇順に格納し、格納
エリアに余りが生じても、該エリアには特に転送処理は
しない。1つの完全な受信データ#1の転送完了を検出
したとき、そのデータ長をデータ長レジスタ8に記憶し
でおき、該READ指令(#1)を終結する。ホストは
、引き続き次のデ−夕を受信するために、新らたなRE
A D指令(#2)を発行する。このREAD指令で−
、通信制御装置t;1、該指令が示すデータエリアの先
頭アドレスに、まず先にデータ長レジスタ8に記憶して
おいた前受信データ#1のデータ長を転送し、引き続き
受信データ#2を転送する。1つの完全な受信データ#
2の転送完了を検出したとき、そのデータ長を記1息し
、上記処理をくり返す。次に、最後のデータを受信した
ときの処理は、次のように[7て行:/2′1−)fす
る。即ち、最後の受信データを転送したR E A I
)指令に引き続いて光行されたR E A D指令で&
、J、 、転送すべき受信データはないので、直前の受
信データのデータ長のみを転送する。このようにして本
発明では、n個の受信データを(n十1ン個のRE A
 D指令を用いて処理することができる。
Thereafter, the received data #l is stored in ascending order until the end, and even if there is a surplus in the storage area, no particular transfer process is performed on that area. When the completion of transfer of one complete received data #1 is detected, the data length is stored in the data length register 8, and the READ command (#1) is terminated. The host sends a new RE to continue receiving the next data.
Issue AD command (#2). With this READ command -
, communication control device t;1, first transfers the data length of the previous received data #1 stored in the data length register 8 to the start address of the data area indicated by the command, and then transfers the data length of the previously received data #2. Forward. 1 complete received data #
When the completion of transfer 2 is detected, the data length is recorded and the above process is repeated. Next, when the last data is received, the processing is as follows: [line 7:/2'1-)f. That is, the R E A I that transferred the last received data
) command followed by the R E A D command.
,J, Since there is no received data to be transferred, only the data length of the immediately previous received data is transferred. In this way, in the present invention, n pieces of received data are transferred to (n11 pieces of RE A
It can be processed using the D command.

〔発明の効果〕〔Effect of the invention〕

本発明tま、RE A D指令の実行に関し、アドレス
の減算処理は不要であるため、アドレスの昇順にしかデ
ータの転送を行なうことができない簡単な構成の装置で
も実施することができ、受信データおよびデータ長転送
のための1ζEAD指令の数をほとんど増やすことなく
 そのデータとデータ長をホストへ通知することができ
る○また、通信制御装置とホストとの間のインクラクシ
ョンが減り、負荷の集中を避けることができ、能率のよ
いシステムを構築することができる。
According to the present invention, since there is no need for address subtraction processing in executing the RE A D command, it can be carried out even by a device with a simple configuration that can only transfer data in ascending order of addresses, and the received data The data and data length can be notified to the host without increasing the number of 1ζEAD commands for data length transfer.In addition, the interference between the communication control device and the host is reduced, reducing the concentration of load. This can be avoided and an efficient system can be built.

本発明で首うデータ長とはデータ長そのものである必要
はなく、データ長に一意に対応する情報でよいことは自
明である。さらにデータ長を転送するときにデータ長以
外の付加情報をも転送することも可能である。
It is obvious that the data length used in the present invention does not have to be the data length itself, and may be information that uniquely corresponds to the data length. Furthermore, when transferring the data length, it is also possible to transfer additional information other than the data length.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例システムの構成図、第2図はRE
AD指令の機能説明図、第3図はデータおよびデータ長
の格納動作の説明図、第4図は通信制御装置が1つのR
EAD指令について実行する動作のフロー図でめる0 図中、1はホスト、2は通信制御装置、3,4はモデム
、5は端末、6は受信データバッファ、7tま制911
1都、8はデータ長レジスタ、9は転送パツンア、10
はデータアドレスレジスタを表わす。 特許出願人 富士通株式会社 代理人弁理士 長谷用文廣(外1名) −1: 第 1 図 第 2 図
Figure 1 is a configuration diagram of the system according to the present invention, and Figure 2 is the RE
Figure 3 is an explanatory diagram of the function of the AD command, Figure 3 is an explanatory diagram of the storage operation of data and data length, and Figure 4 is an explanation diagram of the function of the AD command.
A flowchart of the operations executed regarding the EAD command. In the figure, 1 is the host, 2 is the communication control device, 3 and 4 are the modem, 5 is the terminal, 6 is the receive data buffer, and 7t control 911
1 capital, 8 data length register, 9 transfer pattern, 10
represents the data address register. Patent applicant Fujitsu Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) -1: Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] ホストからの指令にもとづき動作する通信制御装置にお
いて、回線から受信する一連の又は複数のブロックに分
割されている受信データのそれぞれのデータ長をホスト
に通知するための受信データ長保持手段をそなえ、n番
目の受信データをホスト内に設けられた受信データバッ
ファへ転送するためのホストからのREAD指令をRE
AD#nとしたとき、該RE A D #n指令で示さ
れる上記メモリのデータ格納アドレスに、(n−1)番
目に受信した受信データのデータ長を上記受信データ長
保持手段から転送して先に格納し、その後上記データ格
納アドレスに続くアドレスにn番目に受信した受信デー
タを順次格納することにより、データ回線からの受信デ
ータおよびそのデータ長をホストに転送することを特徴
とするデータ転送方式。
A communication control device that operates based on instructions from a host, comprising a received data length holding means for notifying the host of the data length of each piece of received data received from a line and divided into a series or a plurality of blocks, RE the READ command from the host to transfer the nth received data to the receive data buffer provided in the host.
When AD#n, the data length of the (n-1)th received data is transferred from the received data length holding means to the data storage address of the memory indicated by the RE A D #n command. A data transfer characterized in that received data from a data line and its data length are transferred to a host by first storing the received data and then sequentially storing the nth received data in an address following the data storage address. method.
JP57166073A 1982-09-24 1982-09-24 Data transfer system Granted JPS5955528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57166073A JPS5955528A (en) 1982-09-24 1982-09-24 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57166073A JPS5955528A (en) 1982-09-24 1982-09-24 Data transfer system

Publications (2)

Publication Number Publication Date
JPS5955528A true JPS5955528A (en) 1984-03-30
JPS6360428B2 JPS6360428B2 (en) 1988-11-24

Family

ID=15824475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57166073A Granted JPS5955528A (en) 1982-09-24 1982-09-24 Data transfer system

Country Status (1)

Country Link
JP (1) JPS5955528A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62152244A (en) * 1985-12-26 1987-07-07 Yamatake Honeywell Co Ltd Communication control system
JPS62152252A (en) * 1985-12-26 1987-07-07 Yamatake Honeywell Co Ltd Communicating control system
US4894987A (en) * 1988-08-19 1990-01-23 Ap Parts Manufacturing Company Stamp formed muffler and catalytic converter assembly

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62152244A (en) * 1985-12-26 1987-07-07 Yamatake Honeywell Co Ltd Communication control system
JPS62152252A (en) * 1985-12-26 1987-07-07 Yamatake Honeywell Co Ltd Communicating control system
JPH0377700B2 (en) * 1985-12-26 1991-12-11 Yamatake Honeywell Co Ltd
JPH0418500B2 (en) * 1985-12-26 1992-03-27 Yamatake Honeywell Co Ltd
US4894987A (en) * 1988-08-19 1990-01-23 Ap Parts Manufacturing Company Stamp formed muffler and catalytic converter assembly

Also Published As

Publication number Publication date
JPS6360428B2 (en) 1988-11-24

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