JPS6375853A - Memory device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an unexpected accident by arbitrarily reading and writing data in a switched and set read/write address range and deciding the classification of a mounted memory element according as the normal operation is performed or not and switching and connecting the input and the output of this element to prescribed states in accordance with decision result. CONSTITUTION:In case of access to a memory element 1, a processor 2 sets an FF 3, and the output is inputted to NAND gates G1 of switching connection gates 4 and 5 of upper address signals A14 and A13, and the inverted output is inputted NAND gates G2 of gates 4 and 5. The signal A14 and a memory write signal MWRO are inputted to gates G1 of gates 4 and 5 respectively, and signal '1' and the signal A14 are inputted to gates G2 of gates 4 and 5, and outputs of gates G1 and G2 of gates 4 and 5 are inputted to address signal input terminals X and Y of the element 1 through negative logic OR gates G3.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a memory device.

[Prior Art] Conventionally, a read-only memory element (ROM) and a read/write memory element (1"
There is a memory Ruff which is used interchangeably with (AM) at the same mounting location on the board.

In such a memory device, the address bus and f-
It is necessary to switch the connection relationship with Tabas to the specified state.

Therefore, for example, if a 256-bit memory/n capacity ROM or RAM is installed, it can be used.
As shown in the conventional circuit configuration of FIG.
Data signals DO to D7.A and 1B are output. Among the memory write signal MWRO address signals AO to A14,
The upper address signal A14 and memory write signal MWRO are switched by switches SW1 to SW4 depending on whether 1A and 1B are set to ROM or RAM.

In other words, if ROM is mounted on 1A, switch SW
3 and SW4 are switched as shown.

[Problems to be solved by the invention] However, since the input and output of the memory element is manually switched, the switching setting operation is troublesome, and if the switching setting is forgotten, an unexpected accident may occur. There was a problem that this occurred.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device that automatically performs input/output related switching settings to prevent unexpected accidents from occurring.

Means for Solving Problem E J The present invention switches and sets data read/write address ranges, reads arbitrary data in each read/write address range, and determines whether or not a normal read/write operation has been performed. The device is provided with a determining means for determining the type of the currently mounted memory element, and a switching means for switching and connecting the input and output of the mounted memory element to a specified state based on the result of the determination.

[Operation] The determination means sets an arbitrary address range within the address range that can be specified by the address signal after the memory element is mounted,
Any data can be read within this address range. Then, if the written data and read data match, RA
It is determined that the memory element is M, and the input/output signal lines of the memory element are switched and connected in a prescribed input/output relationship. However, if the written data and the read data do not match, it is determined that it is a ROM, and the connection is switched to a prescribed input/output relationship.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention, with 256
A circuit is shown in which bits of ROM or RAM are exchanged and used.

In the figure, it is unclear whether the memory element 1 is a ROM or a RAM when the power is turned on.

Therefore, the processor 2 that accesses this memory element 1
sends a set signal 5ETI to the flip-flop 3 to set the flip-flop 3.

The set output Q of the flip-flop 3 is commonly input to the Nant gate G1 of the switching connection gate 4.5 of the upper address signals A14 and A13, and the inverted set output is commonly input to the other Nant gate G2. The address signal A14 is input to the other input of the Nant gate G1 of the switching connection gate 4, and the address signal A1'' is input to the other input of the Nant gate G2. The memory write signal M W RO is input to the other input of the Nant gate G2, and the address signal A14 is input to the other input of the Nant gate G2.

And also, the Nantes gate G1 of the switching connection gate 3.
The output of G2 is connected to the input/output terminals X of the memory element 1 via a negative logic OR gate G3, and the output of one of the switching connection gates 5 is connected to the Nant gate G1. The output of G2 is also connected to the input terminal Y of the memory element 1 via a negative logic OR gate G3.

Therefore, if the input terminal X is the input terminal for the RAM address signal A14, and Y is the input terminal for the memory write signal f'';
A14 and MWRO are connected to the input terminals X and Y of memory element 1.
You can enter the following information. Therefore, processor 2 has 25
An arbitrary address range smaller than 6 bits is set using address signals eA14 to AO, and arbitrary data is written in that address range. Thereafter, data is read in the same address range, and it is detected whether or not it matches the previously read data. If they match, it means that both data reading and reading were performed normally, so it is determined that the memory element 1 mounted at this time is a RAM,
The flip-flop 3 is kept in the set state for subsequent access.

However, if the stored data and the read data do not match, it is determined that the memory element 1 mounted at this time is a ROM, and the flip-flop 3 is switched to the reset state. Then, 111 II is input to the input terminal X of the memory element 1 via the Nant gate G2 and the OR gate G3 of the switching connection gate 4, and the input terminal Y
is the Nantes gate G2 of the switching connection gate 5; J3
Then, the address signal ¥3iA14 is inputted through the OR gate G3, and the memory becomes usable as a ROM.

Note that 6 in the figure is the address signal A15. which is higher than the address signal @A14. This is a decoder that decodes A16 and provides a chip enable signal CE1 to memory element 1 by a combination of these signals. This is provided to enable selection of memory elements other than the above.

In this embodiment, the switching connection is performed using a gate circuit element, but a relay contact or the like capable of external side υ0 may also be used.

[Effects of the Invention] As explained above, according to the present Komei, the type of the mounted memory element is automatically determined and the connection is switched to the specified input/output relationship, so that manual operation is not required when replacing the memory element. There is no need to perform a switching operation, and unexpected accidents caused by mistakes in the switching operation can be completely prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional configuration. DESCRIPTION OF SYMBOLS 1...Memory element, 2...Processor, 3...Flip-flop, 4.5...Switch connection gate. Figure 1

Claims (1)

[Claims] In a memory device that uses a read-only memory element and a read-write memory element with the same storage capacity and the same shape interchangeably at the same mounting location on the board, the data read/write address range is switched and set, and arbitrary data can be stored in each read/write address range. determining means for determining the type of the currently installed memory element based on whether or not normal reading and writing operations have been performed, and determining the input/output of the installed memory element based on the determination result. A memory device comprising: switching means for switching connection to a specified state.