JPS6375851A - Memory device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an unexpected accident by arbitrarily reading and writing data in a switched and set read/write address range and deciding the storage capacity of a mounted memory element according as the normal operation is performed or not and switching and connecting the input and the output of this element to prescribed states in accordance with the discrimination result. CONSTITUTION:In case of access to a memory element 1, a processor 2 sets an FF 3, and its output Q is inputted to NAND gates G1 of switching connection gates 4 and 5 of upper address signals A14 and A13, and signals A14 and A13 are inputted to the other inputs of gates G1. The inverted set output of the FF 3 is inputted to NAND gates G2 of gates 4 and 5, and signal '1' is inputted to a gate G2 of the gate 4 and a chip enable signal CE2 is inputted to a gate G2 of the gate 5, and outputs of gates G1 and G2 of gates 4 and 5 are inputted to address signal input terminals X and Y of the element through a negative logic OR gate G3.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a memory device.

[Prior Art] Conventionally, there is a memory device in which memory elements of the same shape but with different storage capacities are used by replacing them at the same mounting location on a board.

In such a memory device, it is necessary to switch the connection relationship with the address bus and the data bus to a specified state according to the input/output terminal arrangement of the actually mounted memory element.

Therefore, for example, in a device in which memory elements with a storage capacity of 64 bits and 256 bits are exchanged, data signals input and output from the memory element 1 of 256 bits are input and output, as shown in the conventional circuit configuration of Fig. 2. DO~D9, memory read signal qMRD, memory write signal MWR, chip enable signal CE1. GE2. Address signal AO~A14
Among them, the upper address signal A14.64 is not used when a 64-bit memory element is mounted. Switches sw1 and sw2 are provided to switch and connect A13 to 1'' for A14, and to ecs2 for A13, and by manually switching these switches sw1 and sw2, pins 1 to 256 are connected to 64. The memory elements of pins 1 to 1 are replaced to make them usable.

[Problems to be solved by the invention] However, since the input and output of the memory element is manually switched, the switching setting operation is troublesome, and if the switching setting is forgotten, an unexpected accident may occur. There was a problem that this occurred.

An object of the present invention is to automatically perform input/output related switching settings to prevent unexpected accidents from occurring. The goal is to provide f.

[Means for Solving the Problems] The present invention switches and sets the address range for reading and writing data, reads and writes arbitrary data in each read/write address range, and performs normal reading and writing operations. flJl stabilization, which determines the storage capacity of the currently mounted memory element based on whether the It is something that

[Operation] The determination means sets, for example, the uppermost address range among the address ranges that can be specified by the address signal depending on the mounting of the memory element, and reads and writes arbitrary data in this address range. If the data entered in p1 and the read data match, it is determined that the memory element has a storage capacity that has an address space corresponding to the address range set at this time, and input/output signal lines of the memory element are connected to specified input/output signal lines. Switch and connect to the output. However, if the written data and the read data do not match, the next address range is set, and arbitrary data is read and written again to determine the storage capacity.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. Here, a circuit is shown in which memory elements of 64 bits and 256 bits are used interchangeably.

In the figure, when the power is turned on, it is unclear whether the memory element 1 has a storage capacity of 64 bits or 256 bits. Therefore, this memory element 1
The processor 2 that accesses the flip-flop 3 sends a set signal 5ET1 to the flip-flop 3 to set the flip-flop 3.

The set output Q of the flip-flop 3 is commonly input to the Nant gate G1 of the switching connection gate 4.5 of the upper address signals A14 and A13, and the inverted set output is commonly input to the other Nant gate G2. The address signal A14 is input to the other input of the Nant gate G1 of the switching connection gate 4, and "1" is input to the other input of the Nant gate G2. Further, an address signal A13 is input to the other input of the Nant gate G1 of the switching connection gate 5, and a signal GE2 is input to the other input of the Nant gate G2. And also, the Nantes gate G1 of the switching connection gate 3. The output of G2 is connected to the address signal Pi of memory element 1 via negative logic OR gate G3.
The outputs of the Nandt gates G1 and G2 of one switching connection gate 5 are also connected to the input/output terminal of A14, and the address signal QA1 of the memory element 1 is also connected to the input/output terminal of the memory element 1 via the negative logic OR gate G3.
It is connected to the input terminal of 3.

In the case of a 64-bit memory element, input/output terminals for address signals A14 and A13 do not exist, so they are indicated by X and Y in the figure.

Therefore, when the flip-flop 3 enters the set state, the address signal input terminal X of the memory element 1.

Y is now in a state where A14 and A13 can be input. Therefore, processor 2 assigns an address range larger than 64 bits and smaller than 256 bits to address signals /M4 to A.
Set with O, and write any data in that address range. Thereafter, data is read in the same address range, and it is detected whether it matches the previously read data. If they match, it means that an address space actually exists in the address range of 64 bits or more, so it is determined that the memory element 1 installed at this time has a storage capacity of 256 bits, and the flip-flop 3 is kept in the set state for subsequent accesses.

However, if the input/output data and the read data do not match, it means that there is no address space in the address range from 64 bits onwards, so the memory element 1 installed at this time is 64 bits It is determined that the storage capacity is sufficient, and the flip-flop 3 is switched to the reset state.

Then, 1'' is input to the address signal input terminal X of the memory element 1 via the Nant gate G2 and OR gate G3 of the switching connection gate 4, and 1'' is input to the address signal input terminal Y through the Nant gate G2 and the Nant gate G2 of the switching connection gate 5. The signal ecE2 is inputted via the OR gate G3, and the address space of the memory element 1 is designated by the address signals A12 to AO of the address bus ADR-Bus.

Note that 6 in the figure indicates the address signal A15. which is higher than the address signal A14. This is a decoder that decodes A16 and provides a chip enable signal CEI to memory element 1 based on a combination of these signals. This is provided to enable selection of memory elements other than the above.

In this embodiment, the input/output relationship of the memory element 1 is switched only for the address signal, but it is also possible to switch and connect the other signals. Further, although the switching connection is performed using a gate circuit element, a relay contact or the like that can be externally controlled may also be used.

Furthermore, although the storage capacity determination is performed in two stages, it can be easily configured to be performed in three or more stages. In that case, switching connection gates may be provided according to the number of determination stages.

[Effects of the Invention] As explained above, according to the present invention, since the storage capacity of the mounted memory element is automatically determined and the input/output relationship is switched to the specified relationship and the connection is made, when the memory element is replaced, This eliminates the need for manual switching operations, and completely prevents unexpected accidents caused by mistakes in switching operations.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional configuration. DESCRIPTION OF SYMBOLS 1...Memory element, 2...Processor, 3...Flip-flop, 4.5...Switch connection gate. Figure 1

Claims (1)

[Claims] In a memory device in which memory elements of the same shape with different storage capacities are replaced at the same mounting location on a board, data read/write address ranges are switched and set, and arbitrary data can be read and written in each read/write address range. determining means for determining the storage capacity of the currently mounted memory element based on whether or not normal read/write operations have been performed; A memory device comprising: switching means for switching connection.