JPS6375046U - - Google Patents
Info
- Publication number
- JPS6375046U JPS6375046U JP16971486U JP16971486U JPS6375046U JP S6375046 U JPS6375046 U JP S6375046U JP 16971486 U JP16971486 U JP 16971486U JP 16971486 U JP16971486 U JP 16971486U JP S6375046 U JPS6375046 U JP S6375046U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic container
- package
- top surface
- steps
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 2
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案の第１の実施例を示す半導体装
置の断面図、第２図ａ，ｂは本考案の第２の実施
例を示す半導体装置の平面図およびＡ―Ａ′線断
面図である。
１……セラミツク容器、２……素子載置部、３
，４……段、５，６……内部リード、７……外部
リード、８……半導体チツプ、９……金属線、１
０……段、１１……内部リード、１２……ボンデ
イングパツド。
FIG. 1 is a cross-sectional view of a semiconductor device showing a first embodiment of the present invention, and FIGS. 2 a and b are a plan view and a cross-sectional view taken along the line A-A' of the semiconductor device showing a second embodiment of the present invention. It is. 1...Ceramic container, 2...Element placement part, 3
, 4... Stage, 5, 6... Internal lead, 7... External lead, 8... Semiconductor chip, 9... Metal wire, 1
0...stage, 11...internal lead, 12...bonding pad.
Claims (1)
載置部が設けられたセラミツク容器の前記素子載
置部周囲に外周側が内周側より階段状に順次高く
なる複数の段が設けられ前記各段の水平面に設け
られた内部リードが前記セラミツク容器の壁を貫
通して前記外部リードに接続されてなるパツケー
ジと、前記素子載置部に搭載された半導体チツプ
と、前記内部リードと前記半導体チツプのボンデ
イング・パツドとを電気的に接続する金属線とを
含んで構成される半導体装置において、前記パツ
ケージの最内周の段に設けられた前記内部リード
の上面が前記半導体チツプの最上面より低く設け
られたことを特徴とする半導体装置。 A plurality of steps are provided around the device placement portion of a ceramic container in which an external lead is provided on the outside and an device placement portion is provided in the center portion of the inside, and each of the steps is provided such that the outer circumference side is successively higher than the inner circumference side in a stepwise manner. a package in which internal leads provided on the horizontal plane of the ceramic container penetrate the wall of the ceramic container and are connected to the external leads; a semiconductor chip mounted on the element mounting section; In a semiconductor device configured to include a metal wire electrically connected to a bonding pad, the top surface of the internal lead provided at the innermost step of the package is lower than the top surface of the semiconductor chip. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16971486U JPS6375046U (en) | 1986-11-04 | 1986-11-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16971486U JPS6375046U (en) | 1986-11-04 | 1986-11-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6375046U true JPS6375046U (en) | 1988-05-19 |
Family
ID=31103775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16971486U Pending JPS6375046U (en) | 1986-11-04 | 1986-11-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6375046U (en) |
-
1986
- 1986-11-04 JP JP16971486U patent/JPS6375046U/ja active Pending