JPS637470B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite transistor in which a front-stage transistor section and a rear-stage transistor section are arranged side by side on a common substrate constituting a collector layer to form a Darlington circuit.

The Darlington circuit is shown in Figure 1 as an NPN circuit.
As illustrated in the case of using a type transistor, the emitter of the front stage transistor Tr ₁ is directly connected to the base of the rear stage transistor Tr ₂ , and the base of the front stage transistor Tr ₁ is connected to the base terminal B of the entire circuit.
The collectors of both transistors Tr ₁ and Tr ₂ are connected to the collector terminal C of the entire circuit, and the emitter of the subsequent transistor Tr ₂ is connected to the emitter terminal E of the entire circuit.The circuit as a whole is current amplified. It can be handled as a single transistor with a high rate.

Structurally, the two transistors of this Darlington circuit can be constructed integrally on a common substrate constituting the collector, an example of which is shown in FIG.

In the transistor shown in Fig. 2, a semiconductor substrate 1 made of silicon or the like that serves as a collector layer is used as a common N ^- layer, and N-type impurities are diffused on one side of the substrate.
An N ⁺ layer 2 is formed, and a first P layer 3 serving as a first base layer and a second P layer 3 serving as a second base layer are formed on the other side.
Layer 4 is installed in parallel. An N ⁺ layer 6 that becomes a first emitter layer is formed on the first P layer 3, and a second N ⁺ layer 7 that becomes a second emitter layer is formed on the second P type layer 4. There is. Connect collector terminal C from N ⁺ layer 2,
A base terminal B is led out from the P layer 3, and an emitter terminal E is led out from the N ⁺ layer 7. The N ⁺ layer 6 is directly connected to the P layer 4 via a wire 9.
^Here , a common collector layer is constituted by the substrate 1 and the N ⁺ layer 2, and the former stage transistor Tr ₁ in FIG. The collector layer, the base layer made of the P layer 4, and the emitter layer made of the N ⁺ layer 7 constitute the latter stage transistor _Tr2 in FIG.

When a voltage is applied to the Darlington circuit transistor configured in this manner so that the collector terminal C becomes positive with respect to the emitter terminal E and the base terminal B becomes positive with respect to the emitter terminal E, the well-known Darlington circuit is formed. It works as.

Both transistor parts in Fig. 2 have almost the same structure, and both have collector layers with high resistance in order to have high breakdown voltage characteristics, and collector layers and base layers (P layers 3 and 4). Because of the thickness of the transistor, the amplification factor of both transistor portions becomes small, and it has been difficult to obtain a desired large amplification factor even with Darlington circuit connection. Therefore, as shown in FIG. 3, three transistors Tr ₁ , Tr ₂ ,
A _three -stage coupled Darlington circuit consisting of three transistors has also been constructed.

When configuring the Darlington circuit shown in FIG. 3 on a common substrate 1, as shown in FIG. N ⁺ layers 6, 7, and 8 are formed, respectively. The emitter terminal E is derived from the third N ⁺ layer 8 and the second N ⁺ layer 7
is directly connected to the third P layer 5 via a wire 10. Other configurations are basically the same as the Darlington circuit shown in FIG.

However, according to the configurations of FIGS. 3 and 4, although a larger amplification factor can be obtained, there is a drawback that the saturation voltage during conduction increases and power loss increases.

It is therefore an object of the invention to eliminate the above-mentioned drawbacks and to
The object of the present invention is to provide a composite transistor constituting a Darlington circuit that has higher breakdown voltage, higher amplification factor, and higher speed.

To achieve this object, the present invention provides a composite transistor in which a front-stage transistor section and a rear-stage transistor section are arranged side by side on a common substrate constituting a collector layer to form a Darlington circuit.
The base layer of either the front-stage transistor section or the rear-stage transistor section is formed thinner than the other base layer, and the conductivity type of the collector layer is determined in the collector layer of the transistor section with the thinner base layer. The layer is characterized in that layers of different conductivity types are formed and interposed in a lattice or mesh shape so as to face the thin base layer, and are extended so as to be connected to the other thick base layer. be.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 5 shows an embodiment of the present invention.
This embodiment corresponds in circuit diagram to the Darlington circuit shown in FIG. An N ^- layer made of a semiconductor such as silicon is used as a common substrate 1, and an N-type impurity is diffused on one side to form an N ⁺ layer 2, and a P layer 11 is formed in a lattice or mesh pattern on the other side. is forming. Further, on the substrate 1, so as to cover the P layer 11,
The N ^- layer 12 is laminated by epitaxial method or the like.
In the central part of the N ^- layer 12 formed in this way, a P layer 4, which will become the base layer of the subsequent transistor part, is formed relatively thinly to the extent that it does not combine with the P layer 11. Therefore, it is formed relatively thick so as to be combined with the P layer 11 on the outer periphery of the P layer 3 which becomes the base layer. Next, N ⁺ layers 6 and 7, which serve as emitter layers, are formed in the P layers 3 and 4, respectively. After this, from the P layer 3 of the front stage transistor section configured on the outside to the base terminal B
is derived, and the N ⁺ layer 6 is connected to the P layer 4 of the later stage transistor section configured inside via a wire 9. An emitter terminal E is led out from the N ⁺ layer 7 of the latter stage transistor section, and finally a collector terminal C is led out from the common N ⁺ layer 2, thereby completing a Darlington circuit.

In the composite transistor configured in this way, the base layer, that is, the P layer 11 of the former stage transistor part is interposed in the N ^- layer, that is, the collector layer of the latter stage transistor part, in a lattice or mesh shape. Since the flow of electrons that have reached the collector layer flows between the P layers 11, the flow is somewhat hindered, but since the P layer can be made thinner than in conventional structures, high amplification factors and high switching speeds are possible. becomes. The reason for this will be explained in more detail below.

Now, if we consider the case where a positive potential is applied to the emitter terminal E and the collector terminal C and the base terminal B is left open, each base-collector junction of the front-stage transistor section and the rear-stage transistor section is reverse biased. Therefore, the depletion layer spreads across the PN junction. Since the collector layer of the latter transistor section partially has a structure similar to that of a field effect transistor due to the P layers 11 and 3 formed as the base of the former transistor, the emitter-collector voltage increases to a certain value. If it becomes more than that, it will be in a pinch-off state. If the emitter-collector breakdown voltage of the subsequent transistor section without the lattice-like or mesh-like P layer 11 is V _{CEO (NO)} , then the P layer 11 formed in the collector layer can be used at a lower voltage than this. The space between the P layers 11, that is, the space between the P layers 11, so that the N ^- layer is pinched off.
By designing the resistance value of the N ^- layer part, the emitter-collector breakdown voltage of the subsequent transistor part can be increased.
Since it is pinched off in the collector layer before breaking down at v _{CEO (NO)} , the breakdown voltage between emitter E and collector C does not occur at this voltage, and the withstand voltage between the emitter and collector of the subsequent transistor section is improved to V _CEO . be able to.

On the other hand, by designing the front-stage transistor section to have a small amplification factor, a wide base width, and a high breakdown voltage, it is possible to construct a Darlington circuit composite transistor with a high breakdown voltage and a high amplification factor. For example, in a conventional Darlington circuit composite transistor where v _CEO = about 800V, both transistor parts each have a value of 5 or less, making it extremely difficult to achieve a total amplification factor of 20 or more. However, with the structure of the present invention, it is possible to increase the amplification factor of the rear-stage transistor section to 100 or more, and even if the amplification factor of the front-stage transistor section is designed to be about 2, a total amplification factor of 200 or more can be obtained. becomes possible. This amplification factor is calculated when the emitter-collector breakdown voltage v _{CEO (NO)} of the rear-stage transistor section is designed to be 100V, the pinch-off voltage is 80V, and the emitter-collector breakdown voltage v _CEO of the front-stage transistor is set to 800V or more. It is something. In summary, according to the present invention,
This means that it is possible to obtain a Darlington circuit transistor with an emitter-collector breakdown voltage of 800V or more and a high amplification factor of several hundred or more.

Generally, the emitter-collector breakdown voltage v _CEO of a transistor is There is a relationship between Here, h _FE is the current amplification factor, n is a constant, and is 3 to 4 in the NPN diffusion-based type.
v _CBO is the base-collector breakdown voltage. As can be inferred from equation (1), in transistors with conventional structures, withstand voltage and amplification factor have a contradictory relationship, and it has been extremely difficult to obtain a high withstand voltage and a high amplification factor at the same time. However, according to the present invention, it is possible to obtain a composite transistor with high breakdown voltage and high amplification factor. In addition, in the conventional structure, the switching speed was slow due to the need to widen the base width, making it difficult to use at high frequencies, but with the transistor of the present invention, the base width can be narrowed regardless of the withstand voltage, resulting in high switching speed. This also made it possible to speed up the process.

In the transistor of the present invention, by forming a new P layer 11 in the collector layer, the carrier path becomes narrower in that region, but in the transistor shown in FIG. ) formula, it is possible to obtain a higher emitter-collector breakdown voltage, so when a certain withstand voltage is required between the emitter and collector of a Darlington circuit transistor, the collector-base breakdown voltage V is higher than that of a general Darlington circuit transistor. Since _{the CBO} can be lowered, the specific resistance of the collector layer can be lowered. Therefore, it seems that the resistance value of the collector increases as the collector region becomes narrower due to the P layer 11, but in reality, the specific resistance of the collector can be lowered, so the resistance value should not change much. can. Generally, the resistance value R is expressed as R=l/A・ρ (where l is the length, A is the cross-sectional area, and ρ is the specific resistance), so the area A
Even if the length l becomes small and the length l becomes somewhat long, the specific resistance ρ can be made small, so it is possible to design so that the resistance value R does not become large overall. For example, even if the area A is reduced by 40% due to the formation of the P-type layer 11, it is easy to lower the specific resistance by 40%, and the resistance value R can be easily reduced by 40% without changing the length l.
This means that there is no need to increase overall. In particular, in terms of design, it is easy and possible to prevent the P layer 11 formed in a lattice or mesh shape from directly below the emitter (N ⁺ layer), so that the carrier flow is not disturbed. In this way, it is possible to avoid increasing the resistance of the collector layer due to the newly formed P layer 11.

Although the above explanation is for the case where the rear-stage transistor section has a high amplification factor, it is also possible to make the front-stage transistor section a high amplification factor, and an example thereof is shown in FIG.

In the transistor shown in FIG. 6, the positions of the front-stage transistor section and the rear-stage transistor section are exchanged based on the transistor shown in FIG. , a relatively thick P layer 4 is provided in the peripheral portion to serve as a base layer of a subsequent transistor section.
Of course, the N ⁺ layer 6 serving as an emitter layer is formed in the P layer 3, and the N ⁺ layer 7 is formed in the P layer 4. Circuit connection and terminal derivation are performed according to FIG. 5.

It is best to decide whether to use the structure shown in FIG. 5 or the structure shown in FIG. 6 depending on the desired switching speed and secondary fracture resistance. In general, setting the rear stage transistor section to a high amplification factor as shown in Fig. 5 is suitable when high speed is required, and setting the front stage transistor section to a high amplification factor as shown in Fig. 6 is suitable for secondary Suitable when destruction resistance is required. Therefore,
Which structure should be selected depends on the application.

Although the embodiments shown in FIGS. 5 and 6 relate to NPN type transistors, the present invention can be applied to PNP type transistors in exactly the same manner as to NPN type transistors.

PNP type Darlington circuit composite transistor is
The circuit has the configuration shown in FIG. That is, it consists of two PNP type transistors Tr ₁₀ and Tr ₂₀ , the former stage transistor Tr ₁₀ has its base connected to the base terminal B, and the emitter connected to the latter stage transistor Tr ₂₀ .
The collectors are connected to the collector terminals C at the bases of the terminals. The emitter of the latter stage transistor Tr ₂₀ is connected to the emitter terminal E, and the collector is connected to the collector terminal C.

In the Darlington circuit shown in FIG. 7, the embodiment shown in FIG. 8 or 9 may be structurally possible depending on which of the transistors in the front stage and the rear stage is used for a high amplification factor. The embodiment of FIG. 8 corresponds to the NPN type embodiment of FIG. 5, and similarly the embodiment of FIG. 9 corresponds to the embodiment of FIG. 6. In both examples, depending on the change from NPN type to PNP type, the change in NPN type
A substrate 21 made of a P ^- layer is used instead of the substrate 1 made of an N ^- layer, a P ⁺ layer 22 is used instead of the N ⁺ layer 2, and N layers 23 and 24 are used instead of the P layers 3 and 4 which are base layers. , P ⁺ layer 26 instead of N ⁺ layers 6 and 7, which serve as emitter layers.
27, and an N layer 31 is used in place of the grid-like or mesh-like P layer 11. Due to this difference between P type and N type, the direction of current, that is, the flow of electrons, is opposite between NPN type and PNP type, but the above explanation as an NPN type transistor remains unchanged as shown in Figures 8 and 9. This also applies to PNP type transistors.

As described above, according to the present invention, the base layer of either the front or rear transistor section is made thinner than the other base layer, and a collector layer is included in the collector layer of the transistor section with the thinner base layer. By forming and interposing a conductivity type layer different from the thinner base layer in a lattice or mesh shape so as to face the thinner base layer, high breakdown voltage and high amplification factor can be achieved.
Moreover, it is possible to provide a composite transistor constituting a Darlington circuit with high switching speed.

[Brief explanation of the drawing]

Figure 1 is a connection diagram of a two-stage coupled Darlington circuit using NPN transistors, Figure 2 is a vertical cross-sectional view showing the structure of a conventional composite transistor corresponding to the Darlington circuit in Figure 1, and Figure 3 is a A connection diagram of a stage-coupled Darlington circuit, FIG. 4 is a vertical cross-sectional view of a conventional composite transistor corresponding to the Darlington circuit in FIG. 3, and FIGS. 5 and 6 are diagrams according to the present invention corresponding to the Darlington circuit in FIG. FIG. 7 is a vertical cross-sectional view showing different embodiments of the composite transistor.
Connection diagrams of a Darlington circuit using PNP type transistors, FIGS. 8 and 9 are longitudinal sectional views showing different embodiments of the composite transistor according to the present invention corresponding to the Darlington circuit of FIG. 7. 1... Substrate (N ^- layer), 2... N ⁺ layer, 3, 4...
... P layer (base layer), 6, 7 ... N ⁺ layer (emitter layer), 9 ... wire, 11 ... lattice-like or mesh-like P layer, 12 ... N ^- layer, B ... base terminal ,E
...Emit terminal, C...Collector terminal, 21...
... Substrate (P ^- layer), 22 ... P ⁺ layer, 23, 24 ...
N layer (base layer), 26, 27...P ⁺ layer (emitter layer), 29... wire, 31... lattice-like or mesh-like N layer, 32... P ^- layer.

Claims (1)

[Claims] 1. On a common collector layer of a first conductivity type, first and second base layers different from the first conductivity type are arranged in parallel, and on the first base layer, a collector layer of the first conductivity type is provided. A first emitter layer is provided on the second base layer, and a second emitter layer of a first conductivity type is provided on the second base layer, and a collector terminal is connected from the collector layer.
A base terminal is led out from the first base layer and an emitter terminal is led out from the second emitter layer, so that the current flowing through the first emitter layer is connected to the second emitter layer.
In a composite transistor formed by electrically connecting to a base layer of the first and second
one of the base layers is formed thinner than the other, and a second layer different from the collector layer is formed in the collector layer opposite to the thinner base layer.
1. A composite transistor characterized in that a layer of conductivity type is interposed in a lattice or mesh pattern and extended so as to be connected to the other thick base layer.